CHAPTER 3 CPU
3.7.5
Diagram for State Transition in Standby Mode
Figure 3.7-2 shows the state transition diagram in standby mode.
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Diagram for State Transition in Standby Mode
Power turned on
Power-on reset
Oscillation
stabilization wait
reset mode
(10)
Oscillation
stabilization wait
(1)
: Cancellation of reset input
(2)
: Reset sources (multiple)
: Transition to sleep mode by the standby control register (STBC: SLP = 1)
(3)
: External reset input
(4)
: Transition to stop mode by the standby control register (STBC: STP = 1)
(5)
: Interrupt request
(6)
: External interrupt request
(7)
(8) (9)
: Time-base timer overflow (end of oscillation stabilization wait time)
(10) (11)
: External reset input
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Figure 3.7-2 State Transition Diagram
(9)
Reset mode
(1)
(11)
RUN mode
(8)
(7)
Stop mode
(4)
(2)
(3)
(6)
(5)
Sleep mode