Fujitsu F2MC-8L F202RA Hardware Manual page 188

CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER
Table 8.4-1 Explanation of Functions of Each Bit in Capture Control Register (TCCR)
Bit name
CPIF:
bit7 Capture edge detection
flag bit
CFCLR:
bit6 Capture edge detection
flag clear bit
CPIEN:
bit5 Capture interrupt request
enable bit
CCMSK:
bit4 Counter clear mask bit
(at capture operation)
TCMSK:
bit3 Compare match counter
clear mask bit
EDGS1 and EDGS0:
bit2, Capture mode enable/
bit1 edge detection selection
bits
bit0 RESV: Reserved bit
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• This bit is set to "1" when the edge specified by EDGS1 and EDGS0 is
detected.
An interrupt request is output when this bit and the capture interrupt request
enable bit (CPIEN) are "1".
• This bit is used to clear the capture edge detection flag.
• When this bit is "1" at write, the capture edge detection flag is cleared. When
"0", the capture edge detection flag is not affected (remains unchanged).
• This bit is used to allow and prohibit interrupt request output to the CPU.
• An interrupt request is output when this bit and the capture edge detection flag
bit (CPIF) are "1".
• The counter state when a capture match is detected is set.
• When this bit is "0", the counter is cleared. When this bit is "1", the counter is
not cleared.
• The counter state when a compare edge is detected is set.
• When this bit is "0", the counter is cleared. When this bit is "1", the counter is
not cleared.
• These bits are used to allow and prohibit the capture function and select
capture edges.
• When using the 8/16-bit capture timer/counter in the capture mode, set these
bits to a value other than "00
• When the edge set by these bits is input, the capture edge detection flag bit
(CPIF) is set to "1".
• Even if this bit is set to "0" or "1", the operation is not affected. The value
previously written becomes the read value.
Function
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