14.11 Program Example For 8-Bit Serial I/O; Program Example For 8-Bit Serial Output - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 14 8-BIT SERIAL I/O

14.11 Program Example for 8-Bit Serial I/O

This section provides program example for 8-bit serial I/O.
■

Program Example for 8-bit Serial Output

● Processing Specifications
• The 8-bit serial output program outputs 8-bit serial data (55
When serial I/O transfer terminates, an interrupt occurs.
• The program resets transfer data with the interrupt processing routine and outputs it continuously.
• The program operates in accordance with the internal shift clock. This clock is output from the SCK
pin.
• If the shift clock is 32t
MHz oscillation (F
Transfer rate = 12.5 MHz/4/32 = 97.7 kbps, interrupt cycle = 8 × 32 × 4/10 MHz = 81.92 µs
● Coding example
SMR
SDR
SSEL
SIOF
SST
ILR4
INT_V
IRQC
INT_V
;--------------------Main program--------------------------------------------------------------------------
336
when the maximum gear speed (1 instruction cycle = 4/F
INST
), the transfer rate and interrupt cycle are as follows:
CH
EQU 0039H
EQU 003AH
EQU 003BH
EQU SMR:7
EQU SMR:0
EQU 007EH
DSEG ABS
ORG 0FFE2H
DW WARI
ENDS
CSEG
:
CLRI
CLRB SST
MOV ILR4,#11111101B
MOV SDR,#55H
MOV SMR,#01111000B
MOV SSEL,#00000001B
SETB SST
SETI
:
) from the SO pin of the 8-bit serial I/O.
H
; Address of serial mode register
; Address of serial data register
; Address of serial/UART selection register
; Defines the interrupt request flag bit.
; Defines the serial I/O transfer start bit.
; Address of interrupt request setting register 4
; [DATA SEGMENT]
; Sets an interrupt vector.
; [CODE SEGMENT]
; The stack pointer (SP), etc., are already initialized.
; Disables interrupts.
; Stops serial I/O transfer.
; Sets the interrupt level to 1.
; Sets transfer data (55H).
; Clears the interrupt request flag, allows the interrupt
request output, shift clock output (SCK), and serial data
output (SO), selects 32tINST, and sets LSB first.
; Selects the 8-bit serial I/O.
; Starts serial I/O transfer.
; Enables interrupts.
) at the 12.5-
CH