Fujitsu F2MC-8L F202RA Hardware Manual page 238

CHAPTER 9 12-BIT PPG TIMER
Figure 9.6-1 Setting Change during 12-bit PPG Timer Operation
Count by counter
Cycle period setting
(RCR23,24:SCL0 to SCL11)
"H" width setting
(RCR21,22:HSC0 to HSC11)
PPG output pulse waveform
*1:
Because the count interval of the operating counter is less than the changed setting, the setting is
effective only within the cycle.
*2: Because a cycle period less than the count interval of the operating counter is set, synchronization
is not detected and the counter overflows.
*3: Because an "H" width less the count interval of the operating counter is set, synchronization is not
detected until the next cycle.
● Error
Because the counter start by program is asynchronous with the count-up start by the selected count clock,
an error (a time difference) may occur until detection of synchronization of compare values for the "H"
width and for the cycle period with a count by the counter. A major error may shorten the time before the
above synchronization to one count clock cycle.
Figure 9.6-2 illustrates an error (a time difference) before the count operation start.
Count by counter
222
"FFF"
H
*1
*1
"00"
H
Figure 9.6-2 Error before Count Operation Start
0 1
Count clock
1 cycle
Count 0
Error
period
(time
difference)
Counter start
Overflow
*2
* 3
1 period
Extend by overflow
2 3 4