Fujitsu F2MC-8L F202RA Hardware Manual page 228

CHAPTER 9 12-BIT PPG TIMER
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Block Diagram of Circuitry Terminating at the Pin Associated with the 12-bit PPG
Timer
Figure 9.3-1 Block Diagram of Circuitry Terminating at the P37/BZ/PPG Pin
PDR read
PDR read
(when read-modify-write is
performed)
PDR write
DDR write
PUL read
PUL write
Notes:
• If the ON setting of the pull-up resistor is selected by the pull-up setting register, the pin state will be
the "H" level (pull-up state) in stop mode (SPL = 1).
• Because buzzer outputs to the P37/BZ/PPG pin precede 12-bit PPG outputs to this pin, if the pin is
used as the PPG pin, turn the buzzer outputs off and set the RCEN bit such that PPG outputs are
enabled.
212
PDR
Output from
peripheral
Output latch
DDR
Stop mode (SPL = 1)
PUL
Stop mode (SPL = 1)
Output
enabl
from
peripheral
Pull-up resistor
P-ch
Pin
P37/BZ/PPG
N-ch