Operations Of Watchdog Timer Functions - Fujitsu F2MC-8L F202RA Hardware Manual

6.4

Operations of Watchdog Timer Functions

The watchdog timer generates a watchdog reset when the watchdog timer counter
overflows.
■
Operations of Watchdog Timer
● Activating watchdog timer
The watchdog timer is activated when the first time "0101
(WDTC: WTE3 to WTE0) of the watchdog control register.
The watchdog timer cannot be stopped without accepting a reset upon activation.
● Clearing watchdog timer
The watchdog timer counter is cleared the second or subsequent time "0101
control bits (WDTC: WTE3 to WTE0) of the watchdog control register.
When the counter is not cleared within the time interval of the watchdog timer, the counter overflows and
the timer generates the internal reset signal having a period of four instruction cycles.
● Time intervals of watchdog timer
The time interval varies depending on the timing at which the watchdog timer is cleared. Figure 6.4-1
shows the relationship between the clear timings and time intervals of the watchdog timer when output
from the time-base timer is used as the count clock (oscillation frequency: 12.5 MHz).
Minimum time interval
Count clock output from
time-base timer
Watchdog 1-bit counter
Maximum time interval
Count clock output from
time-base timer
Watchdog 1-bit counter
Figure 6.4-1 Clearing Watchdog Timer and Time Interval
Watchdog clear
Watchdog reset
Watchdog clear
Watchdog reset
" is written to the watchdog control bits
B
335.5 ms
Overflow
671.0 ms
CHAPTER 6 WATCHDOG TIMER
" is written to the watchdog
B
Overflow
131