Serial Mode Register (Smr) - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 14 8-BIT SERIAL I/O
14.4.1

Serial Mode Register (SMR)

The serial mode register (SMR) is used to allow and prohibit 8-bit serial I/O operation,
select a shift clock, set a transfer direction, control interrupts, and check interrupt
states.
■
Serial Mode Register (SMR)
Address bit7 bit6
0039 SIOF SIOE SCKE SOE CKS1 CKS0 BDS
H
R/W R/W
R/W : Readable and Writable
: Initial value
320
Figure 14.4-2 Serial Mode Register (SMR)
bit5 bit4 bit3 bit2
R/W R/W R/W R/W
SST
Serial I/O transfer is stopped.
0
1
Serial I/O transfer is in progress. Serial I/O transfer is started or allowed.
BDS
0
LSB first (serial I/O transfer starts at the lowest bit.)
1 MSB first (serial I/O transfer starts at the highest bit.)
CKS1 CKS0
0 0
0 1
1 0
1 1
t : Instruction cycle
INST
SOE
P31/UO/SO is used as a general-purpose port (P31).
0
1 P31/UO/SO is used as a serial data output pin.
SCKE
P30/UCK/SCK is used as a general-purpose port (P30) or the shift
0
clock input pin (SCK).
1
P30/UCK/SCK is used as the shift clock output pin.
SIOE
0
Interrupt request output is prohibited.
1
Interrupt request output is allowed.
SIOF
Serial transfer has not
0
terminated.
Serial transfer has already
1
terminated.
bit1 bit0
Initial value
SST 00000000
B
R/W R/W
Serial I/O transfer start bit
At read
Serial I/O transfer is stopped or
prohibited.
Transfer direction selection bit
Shift clock selection bits
Internal shift clock
External shift clock
Serial data output allowance bit
Shift clock output allowance bit
Interrupt request allowance bit
Interrupt request flag bit
At read
This bit is cleared.
Remains unchanged. This bit does not
affect other bits.
At write
SCK pin
2 t Output
INST
8 t Output
INST
Output
32 t
INST
Input
At write