Appendix A I/O Map - Fujitsu F2MC-8L F202RA Hardware Manual

APPENDIX A I/O Map

APPENDIX A
For the registers of peripheral functions incorporated in the MB89202/F202RA series,
the addresses shown in Table A-1 are assigned.
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I/O Map
Table A-1 I/O Map (1 / 4)
Register
Address
abbreviation
0000
PDR0
H
0001
DDR0
H
0002
H
to
0006
H
0007
SYCC
H
0008
STBC
H
0009
WDTC
H
000A
TBTC
H
000B
H
000C
PDR3
H
000D
DDR3
H
000E
RSFR
H
000F
PDR4
H
0010
DDR4
H
0011
OUT4
H
0012
PDR5
H
0013
DDR5
H
0014
RCR21
H
0015
RCR22
H
0016
RCR23
H
0017
RCR24
H
376
I/O Map
Register name
Port 0 data register
Port 0 data direction register
System clock control register
Standby control register
Watchdog control register
Time-base timer control register
Port 3 data register
Port 3 data direction register
Reset flag register
Port 4 data register
Port 4 data direction register
Port 4 output format register
Port 5 data register
Port 5 data direction register
12-bit PPG control register 1
12-bit PPG control register 2
12-bit PPG control register 3
12-bit PPG control register 4
Read/write
Vacancy
Vacancy
Initial value
R/W XXXXXXXX
W 00000000
R/W 1--11100
R/W 00010---
R/W 0---XXXX
R/W 00---000
R/W XXXXXXXX
W 00000000
R XXXX----
R/W ----XXXX
R/W ----0000
R/W ----0000
R/W -------X
R/W -------0
R/W 00000000
R/W --000000
R/W 0-000000
R/W --000000