Fujitsu F2MC-8L F202RA Hardware Manual page 254

CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
■
Register Associated with Interrupt Generation by External Interrupt Circuit 1 and
Vector Table
Table 10.5-1 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table
Interrupt designation
IRQ0
IRQ1
IRQ2
For interrupt operation, see Section "3.4.2 Steps in the Interrupt Operation ".
■
Exercise Caution when Changing Edge Polarity Selection
When changing edge polarity for INT10 to INT12, always write "0" for the appropriate EIR bit to prevent
unintended interrupt generation.
238
Interrupt level setting register
Register
L01 (bit1)
ILR1 (007B ) L11 (bit3)
H
L21 (bit5)
Bit for setting level
L00 (bit0)
L10 (bit2)
L20 (bit4)
Vector table address
Upper Lower
FFFA FFFB
H H
FFF8 FFF9
H H
FFF6 FFF7
H H