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Table of Contents
Related Manuals for Intel BX80637I53570K
Summary of Contents for Intel BX80637I53570K
- Page 1 ® Desktop 3rd Generation Intel Core™ Processor Family Specification Update June 2013 Revision 012 Reference Number: 326766...
- Page 2 INTELLECTUAL PROPERTY RIGHT. A “Mission Critical Application” is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND...
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Page 3: Table Of Contents
Contents Contents Revision History .......................5 Preface ..........................6 Summary Tables of Changes ..................8 Identification Information ....................13 Errata ..........................20 Specification Changes....................51 Specification Clarifications ...................52 Documentation Changes ....................53 § § Specification Update... - Page 4 Contents Specification Update...
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Page 5: Revision History
June 2012 Interface table • Updated Processor Identification Table • Added errata BV84-BV87 June 2012 • Added Intel Pentium G2120 and G2100T Processors October 2012 • Added Desktop 3rd Generation Intel Core i3-3220,i3-3220T,i3-3225,i3-3240,i3- 3240T,i5-3330,i5-3330S,i5-3330P processors • Added errata BV88-BV91 November 2012 •... -
Page 6: Preface
Volume 3A: System Programming Guide ® Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B: System Programming Guide ® Intel 64 and IA-32 Intel Architecture Optimization Reference Manual http://www.intel.com/ ® Intel 64 and IA-32 Architectures Software Developer’s Manual design/processor/ Documentation Changes specupdt/252046.htm... - Page 7 Nomenclature Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. S-Spec Number is a five-digit code used to identify products.
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Page 8: Summary Tables Of Changes
Summary Tables of Changes The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. - Page 9 LBR, BTM or BTS Records May have Incorrect Branch From Information After an BV26 No Fix EIST/T-state/S-state/C1E Transition or Adaptive Thermal Throttling Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation BV27 No Fix Descriptors FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which...
- Page 10 Errata (Sheet 3 of 5) Steppings Number Status ERRATA BV33 No Fix Clock Modulation Duty Cycle Cannot be Programmed to 6.25% BV34 No Fix Processor May Fail to Acknowledge a TLP Request BV35 No Fix An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain BV36 No Fix...
- Page 11 Errata (Sheet 4 of 5) Steppings Number Status ERRATA The Processor May Not Comply With PCIe* Equalization Preset Reflection BV60 No Fix Requirements for 8 GT/s Mode of Operation BV61 No Fix Processor May Issue PCIe* EIEOS at Incorrect Rate Reduced Swing Output Mode Needs Zero De-emphasis to be Supported in PCIe* BV62 No Fix...
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Page 12: Specification Changes
IA32_MC5_CTL2 is Not Cleared by a Warm Reset CPUID Instruction May Not Report the Processor Number in the Brand String for BV97 NO Fix Intel® Core™ i3-3227U and i5-3337U Processors. BV98 No Fix Performance Monitor Counters May Produce Incorrect Results... -
Page 13: Identification Information
The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, ® or Intel Core™ processor family. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor’s family. - Page 14 Processor Production Top-side Markings (Example) ©'10 BRAND PROC# SLxxx SPEED [COO] [FPO] LOT NO S/N Table 1. Processor Identification (Sheet 1 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache...
- Page 15 Table 1. Processor Identification (Sheet 2 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics (GHz) Frequency 4 core: 3.3 3 core: 3.4...
- Page 16 Table 1. Processor Identification (Sheet 3 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics (GHz) Frequency 4 core: 3.8 3 core: 3.9...
- Page 17 Table 1. Processor Identification (Sheet 4 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics (GHz) Frequency 4 core: N/A...
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Page 18: Core:
Table 1. Processor Identification (Sheet 5 of 6) Core Frequency ® Max Intel (GHz) / Turbo Boost Shared Processor Processor DDR3 (MHz) / Number Stepping Technology L3 Cache Notes Number Signature Processor 2.0 Frequency Size (MB) Graphics (GHz) Frequency 4 core: 3.7 3 core: 3.8... - Page 19 Trusted Execution Technology (Intel TXT) enabled. ® ® ® ® Intel Virtualization Technology for IA-32, Intel 64 and Intel Architecture (Intel VT-x) enabled. ® ® Intel Virtualization Technology for Directed I/O (Intel VT-d) enabled. ® Intel AES-NI enabled. Specification Update...
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Page 20: Errata
Under certain conditions as described in the Software Developers Manual section “Out- of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this... - Page 21 Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be lower than expected. The degree of undercounting is dependent on the occurrences of teption). Intel has not observed this erratum with any commercially available software. Workaround: None identified Status: For the steppings affected, see the Summary Tables of Changes.
- Page 22 BV8. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should be transparent to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of an instruction at the lower canonical boundary (0x00007FFFFFFFFFFF) in 64-bit mode, the LBR return registers will save a wrong return address with bits 63...
- Page 23 None identified. Although the EFLAGS value saved by an affected event (a page fault or an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not identified software that is affected by this erratum. This erratum will have no further effects once the original instruction is restarted because the instruction will produce the same results as if it had initially completed without fault or VM exit.
- Page 24 BV13. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error Problem: A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the Overflow (bit [62]) in the MCi_Status register. A DTLB error is indicated by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in the MCi_Status register.
- Page 25 The MONITOR instruction only functions correctly if the specified linear address range is of the type write-back. CLFLUSH flushes data from the cache. Intel has not observed this erratum with any commercially available software. Workaround: Do not execute MONITOR or CLFLUSH instructions on the local xAPIC address space.
- Page 26 If the segment selector descriptor straddles the canonical boundary, the error code pushed onto the stack may be incorrect. Implication: An incorrect error code may be pushed onto the stack. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 27 Implication: Memory ordering may be violated. Intel has not observed this erratum with any commercially available software. Workaround: Software should ensure pages are not being actively used before requesting their memory type be changed.
- Page 28 Upon detection of a non-zero bit in a reserved field an Intel VT-d fault should be recorded. Due to this erratum the processor does not check reserved bit values for Queued Invalidation descriptors.
- Page 29 0x208 in Remap Engine BAR) by writing 1b through RW1C command (Read Write 1 to Clear) when the F bit is already clear then a spurious interrupt from Intel VT-d (Virtualization Technology for Directed I/O) Remap Engine may be observed.
- Page 30 BV34. Processor May Fail to Acknowledge a TLP Request Problem: When a PCIe root port’s receiver is in Receiver L0s power state and the port initiates a Recovery event, it will issue Training Sets to the link partner. The link partner will respond by initiating an L0s exit sequence.
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Page 31: Branch Instructions
BV38. PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Problem: Under very specific timing conditions, if software tries to disable a PerfMon counter through MSR IA32_PERF_GLOBAL_CTRL (0x38F) or through the per-counter event- select (e.g. MSR 0x186) and the counter reached its overflow state very close to that time, then due to this erratum the overflow status indication in MSR IA32_PERF_GLOBAL_STAT (0x38E) may be left set with no way for software to clear it. - Page 32 This erratum only occurs when IA32_FIXED_CTR0 overflows and the processor and counter are configured as follows: ® • Intel Hyper-Threading Technology is enabled • IA32_FIXED_CTR0 local and global controls are enabled • IA32_FIXED_CTR0 is set to count events only on its own thread (IA32_FIXED_CTR_CTRL MSR (38DH) bit [2] = ‘0).
- Page 33 BV44. IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset Problem: IA32_FEATURE_CONTROL MSR (3Ah) may have random values after RESET (including the reserved and Lock bits), and the read-modify-write of the reserved bits and/or the Lock bit being incorrectly set may cause an unexpected GP fault. Implication: Due to this erratum, an unexpected GP fault may occur and BIOS may not complete initialization.
- Page 34 BV48. 64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI Before Any Data is Transferred Problem: If a REP MOVSB/STOSB is executed in 64-bit mode with an address size of 32 bits, and if an interrupt is being recognized at the start of the instruction operation, the upper 32-bits of RCX, RDI and RSI may be cleared, even though no data has yet been copied or written.
- Page 35 BV52. Instructions Retired Event May Over Count Execution of IRET Instructions Problem: Under certain conditions, the performance monitoring event Instructions Retired (Event C0H, Unmask 00H) may over count the execution of IRET instruction. Implication: Due to this erratum, performance monitoring event Instructions Retired may over count.
- Page 36 Due to this erratum, the receiver return loss for common mode and differential mode may exceed those requirements at certain frequencies. Under laboratory conditions, Intel has observed violations of as much as 1 dB. Implication: The PCI Express Gen3 Base Specification for receiver return loss may be exceeded.
- Page 37 Implication: The processor may send an incorrect number of TS Ordered Sets between two EIEOS Ordered Sets when it initiates Secondary Bus Reset or Link Disable. Intel has not observed any failures with commercially available devices due to this erratum.
- Page 38 Status.Receiver Error Status? field (Bus 0, Device 2, Function 0, 1, 2 and Device 6, Function 0, offset 1D0H, bit 0). Implication: Correctable receiver errors may be incorrectly logged. Intel has not observed any functional impact due to this erratum with any commercially available add-in cards. Workaround: None identified.
- Page 39 BV67. MSR_PKG_Cx_RESIDENCY MSRs May Not be Accurate Problem: If the processor is in a package C-state for an extended period of time (greater than 40 seconds) with no wake events, the value in the MSR_PKG_C{2,3,6,7}_RESIDENCY MSRs (60DH and 3F8H–3FAH) will not be accurate. Implication: Utilities that report C-state residency times will report incorrect data in cases of long duration package C-states.
- Page 40 Due to this erratum, the PCIe root port may not initiate a link speed change during some hardware scenarios causing the PCIe link to operate at a lower than expected speed. Intel has not observed this erratum with any commercially available platform. Workaround: None identified.
- Page 41 63:32. Because this erratum applies only to executions outside 64-bit mode, it applies only to attempts by a 32-bit virtual-machine monitor (VMM) to invalidate translations for a 64-bit guest. Intel has not observed this erratum with any commercially available software.
- Page 42 TS1 ordered sets with the Loopback bit set. Due to this erratum, if two consecutive TS1 ordered sets are received only on certain lanes, the controller may not enter loopback. Implication: Intel has not observed any functional issue with any commercially available PCIe devices. Workaround: None Identified.
- Page 43 PCIe links that perform speed changes while at a reduced link width may be limited to the link width in effect at the time of the speed change. Intel has not observed this erratum with any commercially available devices or platforms.
- Page 44 BV85. Performance-Counter Overflow Indication May Cause Undesired Behavior Problem: Under certain conditions (listed below) when a performance counter overflows, its overflow indication may remain set indefinitely. This erratum affects the general- purpose performance counters IA32_PMC{0-7} and the fixed-function performance counters IA32_FIXED_CTR{0-2}. The erratum may occur if any of the following conditions are applied concurrent to when an actual counter overflow condition is reached: 1.
- Page 45 TLB (Translation Lookaside Buffer) holds a valid translation for that linear address. Implication: Due to this erratum, the system may hang. Intel has not observed this erratum with any commercially available software. Workaround: None identified.
- Page 46 Implication: Self- or cross-modifying code may not execute as expected. Intel has not observed this erratum with any commercially available software. Workaround: None identified. Do not use floating-point stores to modify code.
- Page 47 When this erratum occurs, the processor may be missing the processor number in the brand string. In addition, if the affected processors are paired with the Intel® 7 Series Chipset BD82UM77 chipset, the BIOS may incorrectly report this combination as unsupported.
- Page 48 BV98. Performance Monitor Counters May Produce Incorrect Results Problem: When operating with SMT enabled, a memory at-retirement performance monitoring event (from the list below) may be dropped or may increment an enabled event on the corresponding counter with the same number on the physical core’s other thread rather than the thread experiencing the event.
- Page 49 1, further faults should not generate an interrupt. Due to this erratum, further interrupts may still occur. Implication: Unexpected Invalidation Queue Error interrupts may occur. Intel has not observed this erratum with any commercially available software. Workaround: Software should be written to handle spurious VT-d fault interrupts.
- Page 50 Implication: Software may not be easily able to determine the page offset of the original memory access that caused the EPT violation. Intel has not observed this erratum to impact the operation of any commercially available software. Software requiring the page offset of the original memory access address can derive it by...
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Page 51: Specification Changes
Specification Changes The Specification Changes listed in this section apply to the following documents: ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M ®... -
Page 52: Specification Clarifications
Specification Clarifications The Specification Clarifications listed in this section may apply to the following documents: ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture ® • Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2A: Instruction Set Reference Manual A-M ®... -
Page 53: Documentation Changes
64 and IA-32 Architecture Software Developer's ® Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, Intel and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link below to become familiar with this file. - Page 54 DisplayFamily_Displa DisplayFamily_Display DisplayFamily_Displa DisplayFamily_Display yModel Model yModel Model 0F_xx 06_1C 06_1A 06_1E 06_1F 06_25 06_26 06_27 06_2C 06_2E 06_2F 06_35 06_36 § § Specification Update...