Sequence Input Instructions
3-3-6
OR NOT: OR NOT
Purpose
Ladder Symbol
Variations
Applicable Program Areas
Operand Specifications
Reverses the status of the specified bit and takes a logical OR with the current
execution condition.
Bus bar
Variations
Creates ON Each Cycle OR NOT Result is ON
Creates ON Once for Upward Differentiation (See
note 1.)
Creates ON Once for Downward Differentiation (See
note 1.)
Immediate Refreshing Specification (See note 2.)
Combined
Refreshes Input Bit and Creates ON Once for
Variations
Upward Differentiation (See note 3.)
Refreshes Input Bit and Creates ON Once for
Downward Differentiation (See note 3.)
Note
1. The following variations are supported by only the CS1-H, CJ1-H, CJ1M,
or CS1D CPU Units: @OR NOT, %OR NOT, !@OR NOT, and !%OR NOT.
2. Immediate refreshing is not supported by CS1D CPU Units for Duplex-
CPU Systems.
3. Combined variations are supported by CS1D CPU Units for Single-CPU
Systems and CS1-H, CJ1-H, and CJ1M CPU Units only.
Block program areas
OK
Area
CIO Area
Work Area
Holding Bit Area
Auxiliary Bit Area
Timer Area
Counter Area
Task Flag Area
Condition Flags
Clock Pulses
TR Area
DM Area
EM Area with bank
Indirect DM/EM
addresses in binary
Indirect DM/EM
addresses in BCD
Constants
Data Registers
Step program areas
OK
OK
OR NOT bit operand
CIO 000000 to CIO 614315
W00000 to W51115
H00000 to H51115
A00000 to A95915
T0000 to T4095
C0000 to C4095
TK0000 to TK0031
ER, CY, N, OF, UF, >, =, <, >=, <>, <=, A1, A0
0.02 s, 0.1 s, 0.2 s, 1 s, 1 min
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Section 3-3
OR NOT
@OR NOT
%OR NOT
!OR NOT
!@OR NOT
!%OR NOT
Subroutines
Interrupt tasks
OK
171
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