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Omron CS1G/H-CPUxxH Instructions Manual

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Cat. No. W340-E1-08

SYSMAC CS Series

CS1G/H-CPU@@-EV1

CS1G/H-CPU@@H

CS1D-CPU@@H

SYSMAC CJ Series

CJ1G-CPU@@

CJ1G/H-CPU@@H

CJ1M-CPU@@

Programmable Controllers

INSTRUCTIONS

REFERENCE MANUAL

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Page 1 Cat. No. W340-E1-08 SYSMAC CS Series CS1G/H-CPU@@-EV1 CS1G/H-CPU@@H CS1D-CPU@@H SYSMAC CJ Series CJ1G-CPU@@ CJ1G/H-CPU@@H CJ1M-CPU@@ Programmable Controllers INSTRUCTIONS REFERENCE MANUAL...
Page 2 SYSMAC CS Series CS1G/H-CPU@@-EV1 CS1G/H-CPU@@H CS1D-CPU@@H SYSMAC CJ Series CJ1G-CPU@@ CJ1G/H-CPU@@H CJ1M-CPU@@ Programmable Controllers Instructions Reference Manual Revised September 2002...
Page 4 OMRON. No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is con- stantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice.
Page 6: Table Of Contents
TABLE OF CONTENTS PRECAUTIONS ........Intended Audience ............General Precautions .
Page 7 TABLE OF CONTENTS 3-21 High-speed Counter/Pulse Output Instructions ........3-22 Step Instructions .
Page 8 About this Manual: This manual describes the ladder diagram programming instructions of the CPU Units for CS/CJ- series Programmable Controllers (PLCs). The CS Series and CJ Series are subdivided as shown in the following table. Unit CS Series CJ Series CPU Units CS1-H CPU Units: CS1H-CPU@@H CJ1-H CPU Units: CJ1H-CPU@@H...
Page 9 CS1W-SCB21-V1/41-V1, CS1W-SCU21-V1, CJ1W-SCU41 and Boards to perform serial communications Serial Communications Boards/Units Operation Manual with external devices, including the usage of stan- dard system protocols for OMRON products. SYSMAC WS02-PSTC1-E W344 Describes the use of the CX-Protocol to create CX-Protocol Operation Manual protocol macros as communications sequences to communicate with external devices.
Page 10 PRECAUTIONS This section provides general precautions for using the CS/CJ-series Programmable Controllers (PLCs) and related devices. The information contained in this section is important for the safe and reliable application of Programmable Controllers. You must read this section and understand the information contained before attempting to set up or operate a PLC system.
Page 11: Intended Audience
It is extremely important that a PLC and all PLC Units be used for the speci- fied purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PLC System to the above-mentioned appli- cations.
Page 12 Safety Precautions !WARNING Do not touch any of the terminals or terminal blocks while the power is being supplied. Doing so may result in electric shock. !WARNING Do not attempt to disassemble, repair, or modify any Units. Any attempt to do so may result in malfunction, fire, or electric shock.
Page 13: Operating Environment Precautions
Operating Environment Precautions !Caution Do not touch the Power Supply Unit when power is being supplied or immedi- ately after the power supply is turned OFF. The Power Supply Unit will be hot and you may be burned. Operating Environment Precautions !Caution Do not operate the control system in the following locations: •...
Page 14 Application Precautions • The DeviceNet (CompoBus/D) output area for a DeviceNet (Compo- Bus/D) Master Unit (CIO 0050 to CIO 0099) overlaps with the I/O bit area (CIO 0000 to CIO 0319). Do not use automatic allocations for I/O in any system where allocations to the DeviceNet system will overlap with allocations to I/O Units.
Page 15 Application Precautions • CS1-H, CS1D, CJ1, CJ1-H, and CJ1M CPU Units are shipped with the battery installed and the time already set on the internal clock. It is not necessary to clear memory or set the clock before application, as it is for the CS-series CS1 CPU Units.
Page 16 Application Precautions • The contents of the DM, EM, and HR Areas in the CPU Unit are backed up by a Battery. If the Battery voltage drops, this data may be lost. Provide countermeasures in the program using the Battery Error Flag (A40204) to re-initialize data or take other actions if the Battery voltage drops.
Page 17 Application Precautions • Check switch settings, the contents of the DM Area, and other prepara- tions before starting operation. Starting operation without the proper set- tings or data may result in an unexpected operation. • Check the user program for proper execution before actually running it on the Unit.
Page 18: Conformance To Ec Directives
Concepts EMC Directives OMRON devices that comply with EC Directives also conform to the related EMC standards so that they can be more easily built into other devices or the overall machine. The actual products have been checked for conformity to EMC standards (see the following note).
Page 19 Conformance to EC Directives and other conditions. You must therefore confirm that the overall machine or equipment complies with EC Directives. Relay Output Noise Reduction Methods The CS/CJ-series PLCs conforms to the Common Emission Standards (EN50081-2) of the EMC Directives. However, noise generated by relay out- put switching may not satisfy these Standards.
Page 20 Conformance to EC Directives Circuit Current Characteristic Required element The diode connected in parallel with The reversed dielectric strength value Diode method the load changes energy accumulated of the diode must be at least 10 times by the coil into a current, which then as large as the circuit voltage value.
Page 21: Conformance To Ec Directives
Conformance to EC Directives xxii...
Page 22: Introduction
SECTION 1 Introduction This section provides information on general instruction characteristics as well as the errors that can occur during instruction execution. General Instruction Characteristics ....... . . 1-1-1 Program Capacity .
Page 23: General Instruction Characteristics
Section 1-1 General Instruction Characteristics General Instruction Characteristics 1-1-1 Program Capacity The program capacity tells the size of the user program area in the CPU Unit and is expressed as the number of program steps. The number of steps required in the user program area for each of the CS/CJ-series instructions varies from 1 to 7 steps, depending upon the instruction and the operands used with it.
Page 24 10K steps Note Program capacity for CS/CJ-series PLCs is measured in steps, whereas pro- gram capacity for previous OMRON PLCs, such as the C-series and CV- series PLCs, was measured in words. Basically speaking, 1 step is equivalent to 1 word. The amount of memory required for each instruction, however, is...
Page 25 Section 1-1 General Instruction Characteristics • A downwardly differentiated instruction is executed only once after its execution condition goes from ON to OFF. Variation Instruction type Operation Format Example Non- Output instructions The instruction is exe- Output instruction differentiated (instructions requiring cuted every cycle while executed each cycle an execution condi-...
Page 26 General Instruction Characteristics Section 1-1 1-1-4 Instruction Location and Execution Conditions The following table shows the locations in which instructions can be pro- grammed. The table also shows when an instruction requires an execution condition and when it does not. Refer to SECTION 2 Summary of Instructions for details on specific instructions.
Page 27 General Instruction Characteristics Section 1-1 First operand #0000 Second operand D00000 Specifying Bit Addresses Description Example Instruction example To specify a bit address, specify the word 0001 02 0001 address and bit address directly. Bit 02 @@@@ Word CIO 0001 Bit number Word address Note The word address + bit number format is...
Page 28 Section 1-1 General Instruction Characteristics Description Example Instruction example When the contents of @En@_@@@@@ is between MOV #0001 @E1_00200 0000 and 7FFF (00000 to 32,767), the corre- @E1_00200 sponding word between En@_00000 and 0 1 0 1 En@_32767 is specified. Decimal: 257 Specifies E1_00257.
Page 29 General Instruction Characteristics Section 1-1 Addressing Index Registers Method Description Example Instruction example Directly MOVR(560) moves the PLC memory address of a MOVR 0010 IR0 addressing word or bit to an Index Register (IR0 to IR15). Stores the PLC memory address Index Registers of CIO 0010 in IR0.
Page 30 General Instruction Characteristics Section 1-1 Specifying Constants Method Applicable Data Code Range Example operands format Constant All binary data Unsigned #0000 to #FFFF (16-bit data) and binary data binary within a range ± Signed dec- –32,768 to +32,767 imal Unsigned &...
Page 31 General Instruction Characteristics Section 1-1 The following diagram shows the characters that can be expressed in ASCII. Leftmost bit 1-1-6 Data Formats The following table shows the data formats that can be used in CS/CJ-series PLCs. Name Format Decimal Hexadecimal range range Unsigned...
Page 32 Section 1-1 General Instruction Characteristics Name Format Decimal Hexadecimal range range Floating- 31 30 29 20 19 18 17 point deci- Sign of Exponent Mantissa mantissa Binary Sign Exponent Value = (−1) x 1.[Mantissa] x 2 • Sign (bit 31) 1: negative or 0: positive •...
Page 33: Instruction Execution Checks
Section 1-2 Instruction Execution Checks Instruction Execution Checks 1-2-1 Errors Occurring at Instruction Execution An instruction’s operands and placement are checked when an instruction is input from a Peripheral Device or a program check is performed from a Peripheral Device (other than a Programming Console), but these are not final checks.
Page 34 Instruction Execution Checks Section 1-2 All errors for which the Error Flag or Access Error Flag turns ON is treated as a program error The following table lists program errors. The PLC Setup can be set to stop program execution when one of these errors occurs. Error type Description Related flags...
Page 36: Summary Of Instructions
SECTION 2 Summary of Instructions This section provides a summary of instructions used with CS/CJ-series PLCs. Instruction Classifications by Function......Instruction Functions.
Page 37: Instruction Classifications By Function
Instruction Classifications by Function Section 2-1 Instruction Classifications by Function The following table lists the CS/CJ-series instructions by function. (The instructions appear by order of their function in Section 3 Instructions.) *Instructions or instruction groups marked with a single asterisk are supported by the CS1-H, CJ1-H, CJ1M, and CS1D CPU Units only.
Page 38 Section 2-1 Instruction Classifications by Function Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction tion Timer and Timer TIMER TIMH HIGH-SPEED TMHH ONE-MS counter (with TIMER TIMER instructions timer TTIM ACCUMULA- numbers) TIVE TIMER Timer TIML LONG TIMER MTIM MULTI-OUT- (without PUT TIMER timer...
Page 39 Instruction Classifications by Function Section 2-1 Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction tion Data shift 1-bit shift SHIFT REG- SFTR REVERSIBLE ASLL DOUBLE instructions ISTER SHIFT REG- SHIFT LEFT ISTER ARITHMETIC ARITHMETIC ASRL DOUBLE SHIFT LEFT SHIFT RIGHT SHIFT RIGHT 0000 Hex asynchro- ASFT...
Page 40 Instruction Classifications by Function Section 2-1 Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction tion Symbol Binary add SIGNED DOUBLE SIGNED math BINARY ADD SIGNED BINARY ADD instructions WITHOUT BINARY ADD WITH CARRY CARRY WITHOUT CARRY DOUBLE SIGNED BINARY ADD WITH CARRY BCD add BCD ADD...
Page 41 Instruction Classifications by Function Section 2-1 Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction tion Conversion BCD/Binary con- BCD-TO- BINL DOUBLE BINARY-TO- instructions vert BINARY BCD-TO- DOUBLE BINARY BCDL DOUBLE 2’S COMPLE- NEGL DOUBLE 2’S BINARY-TO- MENT COMPLE- DOUBLE BCD MENT SIGN 16-BIT TO...
Page 42 Section 2-1 Instruction Classifications by Function Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction tion Double-pre- Floating point/ FIXD DOUBLE FIXLD DOUBLE 16-BIT TO cision float- binary convert FLOATING TO FLOATING TO DOUBLE ing- point 16-BIT 32-BIT FLOATING instruc- DBLL 32-BIT TO tions* DOUBLE...
Page 43 Section 2-1 Instruction Classifications by Function Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction tion High-speed MODE CON- HIGH-SPEED CTBL COMPARI- TROL COUNTER PV SON TABLE counter/ READ LOAD pulse out- put instruc- tions** SPED SPEED OUT- PULS SET PULSES PLS2 PULSE OUT- ACCELERA-...
Page 44 Instruction Classifications by Function Section 2-1 Classifica- Sub-class Mnemonic Instruction Mnemonic Instruction Mnemonic Instruction tion Block Define block pro- BPRG BLOCK PRO- BEND BLOCK PRO- program- gram area GRAM BEGIN GRAM END ming Block BPPS BLOCK BPRS BLOCK instructions program start/stop PROGRAM PROGRAM PAUSE...
Page 45: Instruction Functions
Section 2-2 Instruction Functions Instruction Functions 2-2-1 Sequence Input Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code LOAD Indicates a logical start and creates an ON/OFF execution condition Start of logic Bus bar based on the ON/OFF status of the specified operand bit. Not required !@LD Starting...
Page 46 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code AND LOAD Continues on Logic block Logic block Takes a logical AND between logic blocks. rung AND LD Required Logic block A Logic block B Serial connection between logic block A and AND LD logic block B.
Page 47: Sequence Output Instructions
Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code BIT TEST LD TST(350), AND TST(350), and OR TST(350) are used in the pro- Continues on TST(350) gram like LD, AND, and OR; the execution condition is ON when the rung OR TST specified bit in the specified word is ON and OFF when the bit is OFF.
Page 48 Section 2-2 Instruction Functions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DIFFERENTIATE Output DIFD(014) turns the designated bit ON for one cycle when the DOWN DIFD(014) Required execution condition goes from ON to OFF (falling edge). DIFD !DIFD Execution condition B: Bit Status of B...
Page 49 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SINGLE BIT RSTB(533) turns OFF the specified bit in the specified word when the Output RESET (CS1-H, RSTB(533) execution condition is ON. Required CJ1-H, CJ1M, or Unlike the RSET instruction, RSTB(533) can be used to reset a bit in a CS1D only) DM or EM word.
Page 50: Sequence Control Instructions
Instruction Functions Section 2-2 2-2-3 Sequence Control Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code Output Indicates the end of a program. END(001) Not required END(001) completes the execution of a program for that cycle. No instructions written after END(001) will be executed. Execution proceeds to the program with the next task number.
Page 51 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code INTERLOCK Interlocks all outputs between IL(002) and ILC(003) when the execu- Output ILC(003) CLEAR tion condition for IL(002) is OFF. IL(002) and ILC(003) are normally Not required used in pairs.
Page 52 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code MULTIPLE JUMP Output When the execution condition for JMP0(515) is OFF, all instructions JMP0(515) JMP0 Required from JMP0(515) to the next JME0(516) in the program are processed as NOP(000).
Page 53: Timer And Counter Instructions
Instruction Functions Section 2-2 2-2-4 Timer and Counter Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code TIMER Output TIM/TIMX(550) operates a decrementing timer with units of 0.1-s. Required The setting range for the set value (SV) is 0 to 999.9 s for BCD (BCD) and 0 to 6,553.5 s for binary (decimal or hexadecimal).
Page 54 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code ACCUMULATIVE Output TTIM(087)/TTIMX(555) operates an incrementing timer with units of Timer TTIM(087) TIMER input Required 0.1-s. The setting range for the set value (SV) is 0 to 999.9 s for TTIM BCD and 0 to 6,553.5 s for binary (decimal or hexadecimal).
Page 55 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code MULTI-OUTPUT Output MTIM(543)/MTIMX(554) operates a 0.1-s incrementing timer with 8 TIMER MTIM(543) Required independent SVs and Completion Flags. The setting range for the MTIM set value (SV) is 0 to 999.9 s for BCD and 0 to 6,553.5 s for binary (decimal or hexadecimal).
Page 56 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code REVERSIBLE Output CNTR(012)/CNTRX(548) operates a reversible counter. Incre- CNTR(012) COUNTER Required ment input CNTR Decre- Increment input (BCD) ment input Reset CNTRX Decrement input input (Binary) N: Counter (CS1-H, CJ1-H, number CJ1M, or CS1D...
Page 57: Comparison Instructions
Instruction Functions Section 2-2 2-2-5 Comparison Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code Symbol Compari- Symbol comparison instructions (unsigned) compare two values Symbol & options son (Unsigned) LD: Not (constants and/or the contents of specified words) in 16-bit binary LD, AND, OR + =, required data and create an ON execution condition when the comparison...
Page 58 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code Symbol Compari- : Comparison Symbol comparison instructions (double-word, signed) compare two son (Double- values (constants and/or the contents of specified double-word data) in data 1 LD: Not word, signed) signed 32-bit binary (8-digit hexadecimal) and create an ON execution required...
Page 59 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code TABLE COM- Output Compares the source data to the contents of 16 words and turns TCMP(085) PARE Required ON the corresponding bit in the result word when the contents are TCMP equal.
Page 60 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code AREA RANGE Compares the 16-bit unsigned binary value in CD (word contents or Output ZCP(088) COMPARE (CS1- constant) to the range defined by LL and UL and outputs the results to Required H, CJ1-H, CJ1M, the Arithmetic Flags in the Auxiliary Area.
Page 61: Data Movement Instructions
Instruction Functions Section 2-2 2-2-6 Data Movement Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code MOVE Output Transfers a word of data to the specified word. MOV(021) Required @MOV Source word !MOV !@MOV S: Source D: Destination Bit status not changed.
Page 62 Section 2-2 Instruction Functions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code MOVE DIGIT Output Transfers the specified digit or digits. (Each digit is made up of 4 bits.) MOVD(083) MOVD Required @MOVD S: Source word or data C: Control word D: Destination word MULTIPLE BIT...
Page 63 Section 2-2 Instruction Functions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE DATA Output Exchanges the contents of a pair of consecutive words with another XCGL(562) EXCHANGE Required pair of consecutive words. XCGL @XCGL E1+1 E2+1 E1: 1st exchange word E2: Second exchange word...
Page 64: Data Shift Instructions
Instruction Functions Section 2-2 2-2-7 Data Shift Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SHIFT REGISTER Output Data Operates a shift register. SFT(010) input Required St+1, St+2 Shift input Reset input Lost Status of data input for each St: Starting word shift input E: End word...
Page 65 Section 2-2 Instruction Functions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE SHIFT Output Shifts the contents of Wd and Wd +1 one bit to the left. ASLL(570) LEFT Required ASLL Wd+1 @ASLL Wd: Word ARITHMETIC Output Shifts the contents of Wd one bit to the right. ASR(026) SHIFT RIGHT Required...
Page 66 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code ROTATE RIGHT Output Shifts all Wd bits one bit to the right not including the Carry Flag (CY). WITHOUT RRNC(575) Required The contents of the rightmost bit of Wd shifts to the leftmost bit and to CARRY the Carry Flag (CY).
Page 67 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SHIFT N-BITS Output Shifts the specified 16 bits of word data to the left by the specified NASL(580) LEFT Required number of bits. NASL @NASL D: Shift word Shift n-bits C: Control word Contents of...
Page 68: Increment/Decrement Instructions
Section 2-2 Instruction Functions 2-2-8 Increment/Decrement Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code INCREMENT Output Increments the 4-digit hexadecimal content of the specified word by 1. BINARY ++(590) Required Wd: Word DOUBLE INCRE- Output Increments the 8-digit hexadecimal content of the specified words by ++L(591) MENT BINARY Required...
Page 69: Symbol Math Instructions
Instruction Functions Section 2-2 2-2-9 Symbol Math Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SIGNED BINARY Output Adds 4-digit (single-word) hexadecimal data and/or constants. +(400) ADD WITHOUT Required CARRY (Signed binary) (Signed binary) CY will turn ON when there (Signed binary) Au: Augend word is a carry.
Page 70 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE BCD Output Adds 8-digit (double-word) BCD data and/or constants. +BL(405) ADD WITHOUT Required CARRY (BCD) Au +1 @+BL (BCD) Ad+1 CY will turn (BCD) Au: 1st augend ON when there word is a carry.
Page 71 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SIGNED BINARY Output −C(412) Subtracts 4-digit (single-word) hexadecimal data and/or constants SUBTRACT Required with the Carry Flag (CY). (Signed binary) WITH CARRY –C @–C (Signed binary) − Mi: Minuend word CY will turn Su: Subtrahend...
Page 72 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE BCD Output Subtracts 8-digit (double-word) BCD data and/or constants with the − SUBTRACT BCL(417) Required Carry Flag (CY). WITH CARRY (BCD) Mi +1 –BCL @–BCL (BCD) Su+1 −...
Page 73 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code BCD MULTIPLY Output Multiplies 4-digit (single-word) BCD data and/or constants. *B(424) Required (BCD) × (BCD) Md: Multiplicand (BCD) R +1 word Mr: Multiplier word R: Result word DOUBLE BCD Output Multiplies 8-digit (double-word) BCD data and/or constants.
Page 74: Conversion Instructions
Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE Output Divides 8-digit (double-word) unsigned hexadecimal data and/or /UL(433) UNSIGNED Required constants. BINARY DIVIDE (Unsigned binary) Dd + 1 @/UL ÷ (Unsigned binary) Dr + 1 Dd: 1st dividend word (Unsigned binary)
Page 75 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code BINARY-TO-BCD Output Converts a word of binary data to a word of BCD data. BCD(024) Required @BCD (BIN) (BCD) S: Source word R: Result word DOUBLE Output Converts 8-digit hexadecimal (32-bit binary) data to 8-digit BCD data.
Page 76 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DATA DECODER Output Reads the numerical value in the specified digit (or byte) in the source MLPX(076) MLPX Required word, turns ON the corresponding bit in the result word (or 16-word @MLPX range), and turns OFF all other bits in the result word (or 16-word range).
Page 77 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DATA ENCODER Output FInds the location of the first or last ON bit within the source word (or DMPX(077) DMPX Required 16-word range), and writes that value to the specified digit (or byte) in @DMPX the result word.
Page 78 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code ASCII TO HEX Output Converts up to 4 bytes of ASCII data in the source word to their HEX(162) Required hexadecimal equivalents and writes these digits in the specified @HEX destination word.
Page 79 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SIGNED BCD- Output Converts one word of signed BCD data to one word of signed binary BINS(470) TO-BINARY Required data. BINS @BINS Signed BCD format specified in C Signed BCD Signed binary C: Control word...
Page 80: Logic Instructions
Instruction Functions Section 2-2 2-2-11 Logic Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code LOGICAL AND Output Takes the logical AND of corresponding bits in single words of word ANDW(034) ANDW Required data and/or constants. @ANDW → : Input 1 : Input 2 R: Result word DOUBLE...
Page 81 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE EXCLU- Output Takes the logical exclusive OR of corresponding bits in double words XORL(612) SIVE OR Required of word data and/or constants. XORL @XORL +1). (I +1) + (I +1).
Page 82: Special Math Instructions
Instruction Functions Section 2-2 2-2-12 Special Math Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code BINARY ROOT Output Computes the square root of the 32-bit binary content of the specified ROTB(620) ROTB Required words and outputs the integer portion of the result to the specified @ROTB result word.
Page 83: Floating-Point Math Instructions
Instruction Functions Section 2-2 2-2-13 Floating-point Math Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code FLOATING TO Output Converts a 32-bit floating-point value to 16-bit signed binary data and FIX(450) 16-BIT Required places the result in the specified result word. @FIX Floating-point data (32 bits)
Page 84 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code FLOATING- Output Multiplies two 32-bit floating-point numbers and places the result in *F(456) POINT MULTIPLY Required the specified result words. Md+1 Multiplicand (floating- point data, 32 bits) ×...
Page 85 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code TANGENT Output Calculates the tangent of a 32-bit floating-point number (in radians) TAN(462) Required and places the result in the specified result words. @TAN Source (32-bit floating-point data) S: 1st source word...
Page 86 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code EXPONENT Output Calculates the natural (base e) exponential of a 32-bit floating-point EXP(467) Required number and places the result in the specified result words. @EXP Source (32-bit floating-point data) S: 1st source...
Page 87: Double-Precision Floating-Point Instructions
Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code FLOATING- Converts the specified single-precision floating-point data (32-bit deci- Output FSTR(448) POINT TO ASCII mal-point or exponential format) to text string data (ASCII) and outputs required (CS1-H, CJ1-H, the result to the destination word.
Page 88 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code 32-BIT BINARY Converts the specified 32-bit signed binary data to double-precision float- Output TO DOUBLE DBLL(844) ing-point data (64 bits) and outputs the result to the destination words. Required FLOATING DBLL...
Page 89 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE Converts the specified double-precision floating-point data (64 bits) from Output RADD(849) DEGREES TO degrees to radians and outputs the result to the result words. Required RADIANS RADD @RADD S: 1st source...
Page 90 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DOUBLE ARC Calculates the angle (in radians) from the tangent value in the specified Output ATAND(856) TANGENT double-precision floating-point data (64 bits) and outputs the result to the Required result words.
Page 91 Instruction Functions Section 2-2 2-2-15 Table Data Processing Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SET STACK Output Defines a stack of the specified length beginning at the specified word SSET(630) SSET Required and initializes the words in the data region to all zeroes. @SSET Internal I/O memory address...
Page 92 Section 2-2 Instruction Functions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DIMENSION Output Defines a record table by declaring the length of each record and the RECORD TABLE DIM(631) Required number of records. Up to 16 record tables can be defined. @DIM Table number (N) Record 1...
Page 93 Section 2-2 Instruction Functions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SWAP BYTES Output Switches the leftmost and rightmost bytes in all of the words in the SWAP(637) SWAP Required range. Byte position is swapped. @SWAP N: Number of words R1: 1st word in range...
Page 94 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code STACK SIZE Counts the amount of stack data (number of words) in the specified stack. Output SNUM(638) READ (CS1-H, required CJ1-H, CJ1M, or CS1D only) SNUM @SNUM TB: First stack address D: Destination...
Page 95: Data Control Instructions
Section 2-2 Instruction Functions 2-2-16 Data Control Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code PID CONTROL Output Executes PID control according to the specified parameters. PID(190) Required Parameters (C to C+8) PV input (S) PID control S: Input word C: 1st parameter word Manipulated variable (D)
Page 96 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DEAD ZONE Output Adds the specified bias to input data and outputs the result. ZONE(682) CONTROL Required Output ZONE @ZONE Positive bias (C+1) Input S: Input word C: 1st limit word D: Output word Negative bias (C)
Page 97 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SCALING 3 Output Converts signed BCD data into signed binary data according to the SCL3(487) SCL3 Required specified linear function. An offset can be input in defining the linear @SCL3 function.
Page 98: Subroutine Instructions
Section 2-2 Instruction Functions 2-2-17 Subroutine Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SUBROUTINE Output Calls the subroutine with the specified subroutine number and SBS(091) CALL Required executes that program. Execution condition ON @SBS N: Subroutine number Main program Subroutine program...
Page 99: Interrupt Control Instructions
Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code GLOBAL SUB- Calls the subroutine with the specified subroutine number and exe- Output ROUTINE CALL GSBS(750) cutes that program. Not required (CS1-H, CJ1-H, CJ1M, or CS1D only) N: Subroutine GSBS number...
Page 100 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code CLEAR Output Clears or retains recorded interrupt inputs for I/O interrupts CLI(691) INTERRUPT (Not Required or sets the time to the first scheduled interrupt for scheduled supported by interrupts.
Page 101: High-Speed Counter And Pulse Output Instructions
Instruction Functions Section 2-2 2-2-19 High-speed Counter and Pulse Output Instructions (CJ1M- CPU22/23 Only) Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code MODE CONTROL INI(880) is used to start and stop target value comparison, to Output change the present value (PV) of a high-speed counter, to Required change the PV of an interrupt input (counter mode), to change @INI...
Page 102 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code PULSE OUTPUT PLS2(887) is used to set the pulse frequency and acceleration/deceler- Output PLS2 ation rates, and to perform pulse output with acceleration/deceleration PLS2 Required (with different acceleration/deceleration rates). Only positioning is pos- @PLS2 sible.
Page 103: Step Instructions
Instruction Functions Section 2-2 2-2-20 Step Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code STEP DEFINE STEP(008) functions in following 2 ways, depending on its position and Output whether or not a control bit has been specified. STEP(008) STEP Required (1)Starts a specific step.
Page 104 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code INTELLIGENT I/O Output Reads the contents of the I/O Unit's memory area. READ IORD(222) Required IORD @IORD Unit number of Special I/O Unit C: Control data S: Transfer Desig- source and nated...
Page 105: Serial Communications Instructions
Instruction Functions Section 2-2 2-2-22 Serial Communications Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code PROTOCOL Output Calls and executes a communications sequence registered in a Serial MACRO PMCR(260) Required Communications Board (CS Series only) or Serial Communications PMCR Unit.
Page 106: Network Instructions
Instruction Functions Section 2-2 2-2-23 Network Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code NETWORK SEND Output Transmits data to a node in the network. SEND(090) SEND Required Destination node @SEND Local node n: No. of send words S: 1st source word D: 1st destination...
Page 107: File Memory Instructions
Instruction Functions Section 2-2 2-2-24 File Memory Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code READ DATA FILE Output Reads the specified data or amount of data from the specified data file FREAD(700) FREAD Required in file memory to the specified data area in the CPU Unit. @FREAD Starting read ad- dress...
Page 108: Display Instructions
Instruction Functions Section 2-2 2-2-25 Display Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DISPLAY Reads the specified sixteen words of extended ASCII and displays the Output MSG(046) MESSAGE message on a Peripheral Device such as a Programming Console. Required @MSG N: Message...
Page 109: Debugging Instructions
Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code HOURS TO Output Converts time data in hours/minutes/seconds format to an equivalent SEC(065) SECONDS Required time in seconds only. @SEC Minutes Seconds S: 1st source Hours word D: 1st destination word Seconds...
Page 110: Failure Diagnosis Instructions
Instruction Functions Section 2-2 2-2-28 Failure Diagnosis Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code FAILURE ALARM Output Generates or clears user-defined non-fatal errors. Non-fatal errors FAL(006) do not stop PC operation. Required Also generates non-fatal errors with the system. @FAL FAL Error Flag ON Corresponding Executed FAL...
Page 111: Other Instructions
Instruction Functions Section 2-2 2-2-29 Other Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code SET CARRY Sets the Carry Flag (CY). Output STC(040) Required @STC CLEAR CARRY Turns OFF the Carry Flag (CY). Output CLC(041) Required @CLC SELECT EM Changes the current EM bank.
Page 112: Block Programming Instructions
Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code DISABLE Disables peripheral servicing during program execution in one of the Output IOSP(287) PERIPHERAL Parallel Processing Modes or Peripheral Servicing Priority Mode. Required SERVICING (CS1-H, CJ1-H, or CJ1M only) IOSP @IOSP ENABLE...
Page 113 Instruction Functions Section 2-2 Instruction Symbol/Operand FunctionS Location Page Mnemonic Execution condition Code BLOCK Block program BPRS Pause and restart the specified block program from another block PROGRAM Required (812) program. RESTART BPRS N: Block program number BPRS(812) executed for block program n. Block program n.
Page 114 Instruction Functions Section 2-2 Instruction Symbol/Operand FunctionS Location Page Mnemonic Execution condition Code CONDITIONAL IF (802) Block program If the execution condition is ON, the instructions between IF(802) and BLOCK Required ELSE(803) will be executed and if the execution condition is OFF, the BRANCHING instructions between ELSE(803) and IEND(804) will be executed.
Page 115 Instruction Functions Section 2-2 Instruction Symbol/Operand FunctionS Location Page Mnemonic Execution condition Code ONE CYCLE AND WAIT(805) Block program If the execution condition is ON for WAIT(805), the rest of the WAIT Required instruction in the block program will be skipped. WAIT Execution Execution...
Page 116 Instruction Functions Section 2-2 Instruction Symbol/Operand FunctionS Location Page Mnemonic Execution condition Code COUNTER WAIT CNTW(814) Block program 1001 Delays execution of the rest of the block program until the specified count CNTW Required has been achieved. Execution will be continued from the next instruction after CNTW(814)/CNTWX(817) when the counter counts out.
Page 117 Instruction Functions Section 2-2 Instruction Symbol/Operand FunctionS Location Page Mnemonic Execution condition Code LOOP Block program 1007 LOOP(809) designates the beginning of the loop program. LOOP Required Execution Execution Execution Execution condition condition condition condition Execution condition Loop repeated LEND LEND (810) LEND(810) or LEND(810) NOT specifies the end of the loop.
Page 118: Text String Processing Instructions
Instruction Functions Section 2-2 2-2-31 Text String Processing Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code MOV STRING Output 1013 Transfers a text string. MOV$(664) MOV$ Required @MOV$ S: 1st source word D: 1st destination word CONCATENATE Output 1015 Links one text string to another text string.
Page 119 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code FIND IN STRING Output 1024 Finds a designated text string from within a text string. FIND$(660) FIND Required Found data @FIND$ → → → S1: Source text string first word S2: Found text string first word...
Page 120 Instruction Functions Section 2-2 Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code EXCHANGE Output 1033 Replaces a designated text string with another designated text string. XCHG$(665) STRING Required XCHG$ @XCHG$ Ex1: 1st exchange word 1 Ex2: 1st exchange word 2 CLEAR STRING Output 1035...
Page 121: Task Control Instructions
Instruction Functions Section 2-2 2-2-32 Task Control Instructions Instruction Symbol/Operand Function Location Page Mnemonic Execution condition Code TASK ON Output 1045 Makes the specified task executable. TKON(820) TKON Required @TKON The specified task's task number The specified task's task number is higher than the local task's task is lower than the local task's task N: Task number...
Page 122: Alphabetical List Of Instructions By Mnemonic
Alphabetical List of Instructions by Mnemonic Section 2-3 Alphabetical List of Instructions by Mnemonic Mnemonic Instruction Function code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification ACCELERATION CON- @ACC TROL ACOS ARC COSINE @ACOS ACOSD DOUBLE ARC @ACOSD COSINE @AND %AND !AND AND <...
Page 123 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction Function code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification AND NOT AND NOT !AND NOT AND TST AND BIT TEST AND TSTN AND BIT TEST AND <= AND LESS THAN OR EQUAL AND <=$ AND STRING LESS...
Page 124 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification BAND DEAD BAND CON- @BAND TROL BINARY-TO-BCD @BCD BCDL DOUBLE BINARY-TO- @BCDL BCDS SIGNED BINARY-TO- @BCDS BCMP UNSIGNED BLOCK @BCMP COMPARE BCMP2 EXPANDED BLOCK...
Page 125 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification CNTRX REVERSIBLE COUNTER CNTW COUNTER WAIT 1001 CNTWX COUNTER WAIT 1001 COLL DATA COLLECT @COLL COLM LINE TO COLUMN @COLM COMPLEMENT COML DOUBLE...
Page 126 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification EXIT (input con- CONDITIONAL BLOCK dition) EXIT EXIT (operand) CONDITIONAL BLOCK EXIT EXPONENT @EXP EXPD DOUBLE EXPONENT @EXPD Mnemonic Instruction FUN code Upward Downward...
Page 127 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification IEND IF END IF NOT (oper- IF NOT and) IF (input condi- tion) IF (operand) INTERLOCK INTERLOCK CLEAR MODE CONTROL @INI INS$ INS$...
Page 128 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification LD <>S LOAD SIGNED NOT EQUAL LD <>SL LOAD DOUBLE SIGNED NOT EQUAL LD <L LOAD DOUBLE LESS THAN LD <S LOAD SIGNED LESS THAN LD <SL...
Page 129 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification LD >=D LOAD DOUBLE FLOATING GREATER THAN OR EQUAL LD >=F LOAD FLOATING GREATER THAN OR EQUAL LD >=L LOAD DOUBLE GREATER THAN OR EQUAL LD >=S...
Page 130 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification MVNL DOUBLE MOVE NOT @MVNL MOVRW MOVE TIMER/ COUNTER PV TO REGISTER Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing...
Page 131 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification OR =D OR DOUBLE FLOAT- ING EQUAL OR =F OR FLOATING EQUAL 329 OR =L OR DOUBLE EQUAL OR =S OR SIGNED EQUAL OR =SL OR DOUBLE SIGNED...
Page 132 Section 2-3 Alphabetical List of Instructions by Mnemonic Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification OUTPUT !OUT OUTB SINGLE BIT OUTPUT @OUTB !OUTB OUT NOT OUTPUT NOT !OUT NOT Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation...
Page 133 Section 2-3 Alphabetical List of Instructions by Mnemonic Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification SUBROUTINE ENTRY SUBROUTINE CALL @SBS SCALING @SCL SCL2 SCALING 2 @SCL2 SCL3 SCALING 3 @SCL3 SDEC 7-SEGMENT @SDEC DECODER SDEL STACK DATA DELETE @SDEL HOURS TO SECONDS 065...
Page 134 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification TIML LONG TIMER TIMLX LONG TIMER TIMW TIMER WAIT TIMWX TIMER WAIT TIMX TIMER TKOF TASK OFF @TKOF 1049 TKON TASK ON @TKON 1045...
Page 135 Section 2-3 Alphabetical List of Instructions by Mnemonic Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification XORL DOUBLE EXCLUSIVE @XORL XORW EXCLUSIVE OR @XORW Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification AREA RANGE COM- PARE ZCPL...
Page 136 Alphabetical List of Instructions by Mnemonic Section 2-3 Mnemonic Instruction FUN code Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification –BCL DOUBLE BCD @–BCL SUBTRACT WITH CARRY –BL DOUBLE BCD @–BL SUBTRACT WITHOUT CARRY –C SIGNED BINARY @–C SUBTRACT WITH CARRY –CL DOUBLE SIGNED...
Page 137: List Of Instructions By Function Code
List of Instructions by Function Code Section 2-4 List of Instructions by Function Code Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification LOAD LD NOT LOAD NOT !LD NOT @AND %AND !AND AND NOT AND NOT !AND NOT OR NOT OR NOT...
Page 138 Section 2-4 List of Instructions by Function Code Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification XORW EXCLUSIVE OR @XORW XNRW EXCLUSIVE NOR @XNRW SET CARRY @STC CLEAR CARRY @CLC TRSM TRACE MEMORY SAMPLING DISPLAY MESSAGE @MSG BINL DOUBLE BCD-TO-...
Page 139 List of Instructions by Function Code Section 2-4 Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification EXTEND MAXIMUM @WDT CYCLE TIME BPRG BLOCK PROGRAM BEGIN IORF I/O REFRESH @IORF RECV NETWORK RECEIVE @RECV MCRO MACRO @MCRO SIGNED BINARY !CPS COMPARE...
Page 140 List of Instructions by Function Code Section 2-4 Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification LD =L LOAD DOUBLE EQUAL OR =L OR DOUBLE EQUAL AND =S AND SIGNED EQUAL LD =S LOAD SIGNED EQUAL --- OR =S OR SIGNED EQUAL AND =SL...
Page 141 List of Instructions by Function Code Section 2-4 Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification AND <= L AND DOUBLE LESS THAN OR EQUAL LD <= L LOAD DOUBLE LESS THAN OR EQUAL OR <= L OR DOUBLE LESS THAN OR EQUAL AND <= S...
Page 142 Section 2-4 List of Instructions by Function Code Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification LD >= S LOAD SIGNED GREATER THAN OR EQUAL OR >= S OR SIGNED GREATER THAN OR EQUAL AND >= SL AND DOUBLE SIGNED GREATER THAN OR EQUAL...
Page 143 Section 2-4 List of Instructions by Function Code Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification OR <>D OR DOUBLE FLOAT- ING NOT EQUAL AND <D AND DOUBLE FLOAT- ING LESS THAN LD <D LOAD DOUBLE FLOATING LESS THAN OR <D...
Page 144 List of Instructions by Function Code Section 2-4 Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification –C SIGNED BINARY @–C SUBTRACT WITH CARRY –CL DOUBLE SIGNED @–CL BINARY SUBTRACT WITH CARRY –B BCD SUBTRACT @–B WITHOUT CARRY –BL DOUBLE BCD @–BL...
Page 145 Section 2-4 List of Instructions by Function Code Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification ACOS ARC COSINE @ACOS ATAN ARC TANGENT @ATAN SQRT SQUARE ROOT @SQRT EXPONENT @EXP LOGARITHM @LOG BINS SIGNED BCD-TO- @BINS BINARY BCDS SIGNED BINARY-TO-...
Page 146 List of Instructions by Function Code Section 2-4 Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification MOVRW MOVE TIMER/ @MOVRW COUNTER PV TO REGISTER XCGL DOUBLE DATA @XCGL EXCHANGE ASLL DOUBLE SHIFT LEFT @ASLL ASRL DOUBLE SHIFT @ASRL RIGHT ROLL...
Page 147 List of Instructions by Function Code Section 2-4 Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification LIFO LAST IN FIRST OUT @LIFO SETR SET RECORD LOCA- @SETR TION GETR GET RECORD @GETR NUMBER SWAP SWAP BYTES @SWAP SNUM STACK SIZE READ...
Page 148 Section 2-4 List of Instructions by Function Code Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification OR >=$ OR STRING GREATER 1040 THAN OR EQUALS LIMIT CONTROL @LMT BAND DEAD BAND @BAND CONTROL ZONE DEAD ZONE @ZONE CONTROL MSKS...
Page 149 List of Instructions by Function Code Section 2-4 Function code Mnemonic Instruction Upward Downward Immediate Page Differentiation Differentiation Refreshing Specification CNTW COUNTER WAIT 1001 TMHW HIGH-SPEED TIMER 1004 WAIT TIMWX TIMER WAIT TMHWX HIGH-SPEED TIMER 1004 WAIT CNTWX COUNTER WAIT 1001 TKON TASK ON...
Page 150: Instructions
SECTION 3 Instructions This section describes each of the instructions that can be used in programming CS/CJ-series PLCs. Instructions are described in order of function, as classified in Section 2 Summary of Instructions. Notation and Layout of Instruction Descriptions ........Instruction Upgrades and New Instructions .
Page 151 Timer and Counter Instructions........... 3-6-1 TIMER: TIM/TIMX(550) .
Page 152 Data Shift Instructions ............3-9-1 SHIFT REGISTER: SFT(010) .
Page 153 3-11 Symbol Math Instructions ............3-11-1 SIGNED BINARY ADD WITHOUT CARRY: +(400) .
Page 154 3-13 Logic Instructions ............. 3-13-1 LOGICAL AND: ANDW(034) .
Page 155 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) ..3-16-1 DOUBLE FLOATING TO 16-BIT: FIXD(841)....... 3-16-2 DOUBLE FLOATING TO 32-BIT: FIXLD(842) .
Page 156 3-19 Subroutines ..............3-19-1 SUBROUTINE CALL: SBS(091) .
Page 157 3-29 Debugging Instructions ............3-29-1 Trace Memory Sampling: TRSM(045) .
Page 158: Notation And Layout Of Instruction Descriptions
Notation and Layout of Instruction Descriptions Section 3-1 Notation and Layout of Instruction Descriptions Instructions are described in groups by function. Refer to 2-3 Alphabetical List of Instructions by Mnemonic for a list of instructions by mnemonic that lists the page number in this section for each instruction.
Page 159 Notation and Layout of Instruction Descriptions Section 3-1 Item Contents Operands Where necessary, the meaning of words and bits used in specific operands, such as control words, is given. Source bit: 00 to 0F (0 to 15 decimal) Destination bit: 00 to 0F (0 to 15 decimal) Operand Specifications The memory areas addresses that can be used each operand are listed in a table...
Page 160 Notation and Layout of Instruction Descriptions Section 3-1 • Operands Indicating Control Numbers (Except for Jump Numbers): The decimal form is given for control numbers, e.g., “0 to 1023” is given for the N operand for the SBS(091) instruction. Examples In the examples, constants are given using the CX-Programmer notation, e.g., operands specifying numeric values are given in decimal for with an &...
Page 161: Instruction Upgrades And New Instructions
Instruction Upgrades and New Instructions Section 3-2 Flag Programming Console label CX-Programmer label <= Less Than or P_LE Equals Flag Always ON Flag ON P_On Always OFF P_Off Flag Instruction Upgrades and New Instructions This section lists the instruction upgrades for CS1 CPU Units with the -EV1 suffix and CS1-H/CJ1-H CPU Units.
Page 162 Section 3-2 Instruction Upgrades and New Instructions DOUBLE FLOATING-POINT MULTIPLY, *D(847) DOUBLE FLOATING-POINT DIVIDE, /D(848) DOUBLE DEGREES TO RADIANS, RADD(849) DOUBLE RADIANS TO DEGREES, DEGD(850) DOUBLE SINE, SIND(851) DOUBLE COSINE, COSD(852) DOUBLE TANGENT, TAND(853) DOUBLE ARC SINE, ASIND(854) DOUBLE ARC COSINE, ACOSD(855) DOUBLE ARC TANGENT, ATAND(856) DOUBLE SQUARE ROOT, SQRTD(857) DOUBLE EXPONENT, EXPD(858)
Page 163: Sequence Input Instructions
Section 3-3 Sequence Input Instructions Sequence Input Instructions 3-3-1 LOAD: LD Purpose Indicates a logical start and creates an ON/OFF execution condition based on the ON/OFF status of the specified operand bit. Ladder Symbol Starting point of block Bus bar Variations Variations Restarts Logic and Creates ON Each Cycle Operand Bit is ON...
Page 164 Sequence Input Instructions Section 3-3 Area LD operand bit Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) , –(– –)IR0 to, –(– –)IR15 Description LD is used for the first normally open bit from the bus bar or for the first nor- mally open bit of a logic block.
Page 165 Section 3-3 Sequence Input Instructions Example Instruction Operand AND LD 000000 OR LD 000001 000002 OR LD 000003 OR LD AND LD LD NOT 000004 000005 OR LD 000100 3-3-2 LOAD NOT: LD NOT Purpose Indicates a logical start and creates an ON/OFF execution condition based on the reverse of the ON/OFF status of the specified operand bit.
Page 166 Sequence Input Instructions Section 3-3 Operand Specifications Area LD NOT bit operand CIO Area CIO 000000 to CIO 614315 Work Area W00000 to W51115 Holding Bit Area H00000 to H51115 Auxiliary Bit Area A00000 to A95915 Timer Area T0000 to T4095 Counter Area C0000 to C4095 Task Flag Area...
Page 167 Sequence Input Instructions Section 3-3 Precautions Immediate refreshing (!) can be specified for LD NOT. An immediate refresh instruction updates the status of the input bit just before the instruction is exe- cuted for Basic Input Units (but not Basic Input Units on Slave Racks or for C200H Group 2 Multi-point Input Units) Example Instruction...
Page 168 Section 3-3 Sequence Input Instructions Operand Specifications Area AND bit operand CIO Area CIO 000000 to CIO 614315 Work Area W00000 to W51115 Holding Bit Area H00000 to H51115 Auxiliary Bit Area A00000 to A95915 Timer Area T0000 to T4095 Counter Area C0000 to C4095 Task Flag Area...
Page 169 Sequence Input Instructions Section 3-3 Example Instruction Operand 000000 000001 000002 000003 000004 AND NOT 000005 OR LD AND LD 000006 3-3-4 AND NOT: AND NOT Purpose Reverses the status of the specified operand bit and takes a logical AND with the current execution condition.
Page 170 Sequence Input Instructions Section 3-3 Area AND NOT bit operand Task Flag Area TK0000 to TK0031 Condition Flags ER, CY, N, OF, UF, >, =, <, >=, <>, <=, ON, OFF, AER Clock Pulses 0.02 s, 0.1 s, 0.2 s, 1 s, 1 min TR Area DM Area EM Area without bank...
Page 171 Sequence Input Instructions Section 3-3 3-3-5 OR: OR Purpose Takes a logical OR of the ON/OFF status of the specified operand bit and the current execution condition. Bus bar Ladder Symbol Variations Variations Creates ON Each Cycle OR Result is ON Creates ON Once for Upward Differentiation Creates ON Once for Downward Differentiation Immediate Refreshing Specification (See note.)
Page 172 Sequence Input Instructions Section 3-3 Description OR is used for a normally open bit connected in parallel. A normally open bit is configured to form a logical OR with a logic block beginning with a LOAD or LOAD NOT instruction (connected to the bus bar or at the beginning of the logic block).
Page 173 Sequence Input Instructions Section 3-3 Variations Variations Creates ON Each Cycle OR NOT Result is ON OR NOT Creates ON Once for Upward Differentiation (See @OR NOT note 1.) Creates ON Once for Downward Differentiation (See %OR NOT note 1.) Immediate Refreshing Specification (See note 2.) !OR NOT Combined...
Page 174 Sequence Input Instructions Section 3-3 Precautions Immediate refresh (!) can be specified for OR NOT. An immediate refresh instruction updates the status of the input bit just before the instruction is exe- cuted from a Basic Input Unit (but not Basic Input Units on Slave Racks or for C200H Group 2 Multi-point Input Units).
Page 175 Sequence Input Instructions Section 3-3 In the following diagram, the two logic blocks are indicated by dotted lines. Studying this example shows that an ON execution condition will be produced when either of the execution conditions in the left logic block is ON (i.e., when either CIO 000000 or CIO 000001 is ON) and either of the execution condi- tions in the right logic block is ON (i.e., when either CIO 000002 is ON or CIO 000003 is OFF).
Page 176 Sequence Input Instructions Section 3-3 Instruction Operand AND LD AND LD 000500 The AND LOAD instruction can be used repeatedly. In programming method (2) above, however, the number of AND LOAD instructions becomes one less than the number of LOAD and LOAD NOT instructions before that. In method (2), make sure that the total number of LOAD and LOAD NOT instructions before AND LOAD is not more than eight.
Page 177 Sequence Input Instructions Section 3-3 The logic block consists of all the instructions from a LOAD or LOAD NOT instruction until just before the next LOAD or LOAD NOT instruction on the same rungs. The following diagram requires an OR LOAD instruction between the top logic block and the bottom logic block.
Page 178 Sequence Input Instructions Section 3-3 Coding Example (2) Instruction Operand 000000 AND NOT 000001 LD NOT 000002 AND NOT 000003 000004 000005 OR LD OR LD 000501 The OR LOAD instruction can be used repeatedly. In programming method (2) above, however, the number of OR LOAD instructions becomes one less than the number of LOAD and LOAD NOT instructions before that.
Page 179 Sequence Input Instructions Section 3-3 Immediate refresh instructions cannot be used for Units on Slave Racks. Instruction variation Mnemonic Function I/O refresh Ordinary LD, AND, OR, LD NOT, The ON/OFF status of the specified bit Cyclic refreshing AND NOT, OR NOT is taken by the CPU with cyclic refresh- ing, and it is reflected in the next instruc- tion execution.
Page 180 Sequence Input Instructions Section 3-3 3-3-10 Operation Timing for I/O Instructions The following chart shows the differences in the timing of instruction opera- tions for a program configured from LD and OUT. Input received Input received Input ↑ received Input ↓...
Page 181 Sequence Input Instructions Section 3-3 Address Instruction Operands 000000 LD 000000 000001 OUT 000002 AND 000001 000003 OUT 000004 AND 000002 000005 OUT 000500 000006 LD 000007 AND 000003 000008 OUT 000501 000009 LD 000010 AND 000004 000011 OUT 000502 000012 LD 000013 AND NOT 000005...
Page 182 Sequence Input Instructions Section 3-3 TR0 to TR15 output A TR bit address cannot be repeated within the same block in a program with many output branches, as shown in the following diagram. It can, however, be Duplication used again in a different block. 3-3-12 NOT: NOT(520) Purpose Reverses the execution condition.
Page 183 Sequence Input Instructions Section 3-3 Input bit status Output bit status CIO 000000 CIO 000001 CIO 000002 CIO 000003 3-3-13 CONDITION ON/OFF: UP(521) and DOWN(522) Purpose UP(521) turns ON the execution condition for the next instruction for one cycle when the execution condition it receives goes from OFF to ON. DOWN(522) turns ON the execution condition for the next instruction for one cycle when the execution condition it receives goes from ON to OFF.
Page 184 Sequence Input Instructions Section 3-3 program section, or a subroutine. Refer to 3-5-3 INTERLOCK and INTER- LOCK CLEAR: IL(002) and ILC(003), 3-5-4 JUMP and JUMP END: JMP(004) and JME(005), and 3-20 Interrupt Control Instructions for details. Examples When CIO 000000 goes from OFF to ON in the following example, CIO 000001 is turned ON for just one cycle.
Page 185 Sequence Input Instructions Section 3-3 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands N: Bit number The bit number must be between 0000 and 000F hexadecimal or between &0000 and &0015 decimal. Only the rightmost bit (0 to F hexadecimal) of the contents of the word is valid when a word address is specified.
Page 186 Sequence Input Instructions Section 3-3 Name Label Operation Equals Flag OFF or unchanged (See note.) Negative Flag OFF or unchanged (See note.) Note In CS1 and CJ1 CPU Units, these are turned OFF. In CS1-H, CJ1-H, and CJ1M CPU Units, these Flags are left unchanged. Precautions TST(350) and TSTN(351) are intermediate instructions, i.e., they cannot be used as right-hand instructions.
Page 187: Sequence Output Instructions
Sequence Output Instructions Section 3-4 In the following example, CIO 000001 is turned ON when CIO 000000 is ON or bit 3 of D00010 is OFF. &3 Sequence Output Instructions 3-4-1 OUTPUT: OUT Purpose Outputs the result (execution condition) of the logical processing to the speci- fied bit.
Page 188 Sequence Output Instructions Section 3-4 Area OUT bit operand Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to ,IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description If there is no immediate refreshing specification, the status of the execution condition (power flow) is written to the specified bit in I/O memory.
Page 189 Sequence Output Instructions Section 3-4 Operand Specifications Area OUT bit operand CIO Area CIO 000000 to CIO 614315 Work Area W00000 to W51115 Holding Bit Area H00000 to H51115 Auxiliary Bit Area A44800 to A95915 Timer Area Counter Area TR Area TR0 to TR15 DM Area EM Area without bank...
Page 190 Sequence Output Instructions Section 3-4 Variations Variations Executed Each Cycle for ON Condition KEEP(011) Executed Once for Upward Differentiation Not supported Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification (See note.) !KEEP(011) Note Immediate refreshing is not supported by the CS1D CPU Units. Applicable Program Areas Block program areas Step program areas...
Page 191 Sequence Output Instructions Section 3-4 S execution condition R execution condition Status of C If S and R are ON simultaneously, the reset input takes precedence. Reset Status of C The set input (S) cannot be received while R is ON. Reset Status of C KEEP(011) has an immediate refreshing variation (!KEEP(011)).
Page 192 Section 3-4 Sequence Output Instructions Output bit C will maintain its Output bit C will be turned previous status in an interlock. OFF in an interlock. KEEP(011) can be used to create flip-flops as shown below. If a holding bit is used for B, the bit status will be retained even during a power interruption.
Page 193 Section 3-4 Sequence Output Instructions the input device) can cause the operand bit of KEEP(011) to be reset. This sit- uation is shown below. Input Unit KEEP 120000 NEVER The operands for KEEP(011) are input in a different order in ladder diagrams and mnemonic code.
Page 194 Sequence Output Instructions Section 3-4 3-4-4 DIFFERENTIATE UP/DOWN: DIFU(013) and DIFD(014) Purpose DIFU(013) turns the designated bit ON for one cycle when the execution con- dition goes from OFF to ON (rising edge). DIFD(014) turns the designated bit ON for one cycle when the execution con- dition goes from ON to OFF (falling edge).
Page 195 Section 3-4 Sequence Output Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –) IR0 to ,15–(– –) IR Description When the execution condition goes from OFF to ON, DIFU(013) turns B ON.
Page 196 Sequence Output Instructions Section 3-4 Examples Operation of DIFU(013) When CIO 000000 goes from OFF to ON in the following example, CIO 001000 is turned ON for one cycle. 001000 1 cycle 1 cycle Operation of DIFD(014) When CIO 000000 goes from ON to OFF in the following example, CIO 001000 is turned ON for one cycle.
Page 197 Sequence Output Instructions Section 3-4 Variations Executed Each Cycle for ON Condition RSET Executed Once for Upward Differentiation @RSET Executed Once for Downward Differentiation %RSET Immediate Refreshing Specification (See note.) !RSET Combined Immediate Refreshing Once for Upward !@RSET Variations Differentiation (See note.) Immediate Refreshing Once for Downward !%RSET Differentiation (See note.)
Page 198 Section 3-4 Sequence Output Instructions Execution condition of RSET Status of B SET and RSET have immediate refreshing variations (!SET and !RSET). When an external output bit has been specified for B in one of these instruc- tions, any changes to B will be refreshed when the instruction is executed and reflected immediately in the output bit.
Page 199 Sequence Output Instructions Section 3-4 Ladder Symbols SETA(530) D: Beginning word N1: Beginning bit N2: Number of bits RSTA(531) D: Beginning word N1: Beginning bit N2: Number of bits Variations Variations Executed Each Cycle for ON Condition SETA(530) Executed Once for Upward Differentiation @SETA(530) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 200 Sequence Output Instructions Section 3-4 Area Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM addresses in @ D00000 to @ D32767 binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 201 Sequence Output Instructions Section 3-4 N2 bits are reset to 0 (OFF). RSTA(531) can be used to turn OFF bits in data areas that are normally accessed by words only, such as the DM and EM areas. Flags Name Label Operation Error Flag ON if N1 isn’t within the specified range of 0000 to 000F.
Page 202 Sequence Output Instructions Section 3-4 Variations Variations Executed Each Cycle for ON Condition SETB(532) Executed Once for Upward Differentiation @SETB(532) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification (See note.) !SETB(532) Combined Executed Once and Bit Refreshed !@SETB(532) Variations Immediately for Upward Differentiation (See note.)
Page 203 Sequence Output Instructions Section 3-4 Area Indirect DM/EM addresses in *D00000 to *D32767 *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants #0000 to #000F (binary) or &0 to &15 Data Registers DR0 to DR15 Index Registers Indirect addressing using ,IR0 to ,IR15 Index Registers...
Page 204 Sequence Output Instructions Section 3-4 Flags Name Label Operation Error Flag ON if N isn’t within the specified range of 0000 to 000F (&0 to &15). OFF in all other cases. Precautions SETB(532) and RSTB(533) cannot set/reset timers and counters. When SETB(532) or RSTB(533) is programmed between IL(002) and ILC(003) or JMP(004) and JME(005), the status of the specified bit won’t be changed if the program section is interlocked or jumped, i.e., when the inter-...
Page 205 Sequence Output Instructions Section 3-4 3-4-8 SINGLE BIT OUTPUT: OUTB(534) Purpose OUTB(534) outputs the status of the instruction’s execution condition to the specified bit. OUTB(534) can control a bit in the DM Area or EM Area, unlike OUT. This instruction is supported by the CS1-H, CJ1-H, CJ1M, and CS1D CPU Units only.
Page 206 Sequence Output Instructions Section 3-4 Area Index Registers Indirect addressing using ,IR0 to ,IR15 Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –) IR0 to, –(– –) IR15 Description When the execution condition is ON, OUTB(534) turns ON bit N of word D.
Page 207: Sequence Control Instructions
Sequence Control Instructions Section 3-5 Sequence Control Instructions 3-5-1 END: END(001) Purpose Indicates the end of a program. Ladder Symbol END(001) Variations Variations Executed Each Cycle for ON Condition END(001) Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks...
Page 208 Sequence Control Instructions Section 3-5 3-5-2 NO OPERATION: NOP(000) Purpose This instruction has no function. (No processing is performed for NOP(000).) Ladder Symbol There is no ladder symbol associated with NOP(000). Variations Variations Executed Each Cycle for ON Condition NOP(000) Immediate Refreshing Specification Not supported Applicable Program Areas...
Page 209 Sequence Control Instructions Section 3-5 Execution Execution condition ON condition OFF Execution condition Normal Outputs Interlocked section execution interlocked. of the program The following table shows the treatment of various outputs in an interlocked section between IL(002) and ILC(003). Instruction Treatment Bits specified in OUT, OUT NOT, or OUTB(534) TIM, TIMX(550), TIMH(015),...
Page 210 Sequence Control Instructions Section 3-5 Item Treatment in Treatment in IL(002)/ILC(003) JMP(004)/JME(005) Bits in OUT, OUT NOT, OUTB(534) All outputs retain their previous status. Status of timer instructions Reset Operating timers (TIM, TIMX(550), (except (TTIM(087), TTIMX(555), TIMH(015), TIMHX(551), TMHH(540), MTIM(543), and MTIMX(554)) TMHHX(552) only) continue timing because the PVs are updated even when the timer instruction isn’t being...
Page 211 Sequence Control Instructions Section 3-5 IL(002) and ILC(003) cannot be nested, as in the following diagram. Examples When CIO 000000 is OFF in the following example, all outputs between IL(002) and ILC(003) are interlocked. When CIO 000000 is ON in the follow- ing example, the instructions between IL(002) and ILC(003) are executed nor- mally.
Page 212 Sequence Control Instructions Section 3-5 CIO 000000 CIO 000000 Normal Outputs execution interlocked Reset Retained Retained 3-5-4 JUMP and JUMP END: JMP(004) and JME(005) Purpose When the execution condition for JMP(004) is OFF, program execution jumps directly to the first JME(005) in the program with the same jump number. JMP(004) and JME(005) are used in pairs.
Page 213 Sequence Control Instructions Section 3-5 Operands N: Jump Number The jump number must be 0000 to 03FF (0 to 1,023 decimal). Operand Specifications Area JMP(004) JME(005) CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959...
Page 214 Sequence Control Instructions Section 3-5 Because all of instructions between JMP(004) and JME(005) are skipped when the execution condition for JMP(004) is OFF, the cycle time is reduced by the total execution time of the skipped instructions. In contrast, NOP(000) processing is performed for instructions between JMP0(515) and JME0(516), so the cycle time is not reduced as much with those jump instructions.
Page 215 Sequence Control Instructions Section 3-5 In block programs, the instructions between JMP(004) and JME(005) are always skipped regardless of the status of the execution condition for JMP(004). Block program section JMP &1 JME &1 JMP(004) and JME(005) pairs must be in the same task because jumps between tasks are not allowed.
Page 216 Sequence Control Instructions Section 3-5 When CIO 000000 is ON in the following example, the instructions between JMP(004) and JME(005) are executed normally. CIO 000000 CIO 000000 &1 Instructions Normal not executed. execution (Outputs re- main un- changed.) &1 3-5-5 CONDITIONAL JUMP: CJP(510)/CJPN(511) Purpose The operation of CJP(510) is the basically the opposite of JMP(004).
Page 217 Sequence Control Instructions Section 3-5 Variations Jumps when OFF/Doesn’t jump when ON CJPN(511) Immediate Refreshing Specification Not supported Variations Executed Each Cycle for ON Condition JME(005) Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Not allowed...
Page 218 Sequence Control Instructions Section 3-5 Operation of CJP(510) When the execution condition for CJP(510) is OFF, no jump is made and the program is executed consecutively as written. When the execution condition for CJP(510) is ON, program execution jumps directly to the first JME(005) in the program with the same jump number. Execution Execution condition OFF...
Page 219 Sequence Control Instructions Section 3-5 The CJP(510) or CJPN(511) instructions will operate normally in block pro- grams. When the execution condition for the CJP(510) is ON or the execution condi- tion for CJPN(511) is OFF, program execution will jump directly to the JME instruction without executing instructions between CJP(510)/CJPN(511) and JME.
Page 220 Sequence Control Instructions Section 3-5 CIO 000000 CIO 000000 &1 Instructions Normal execution executed. (Outputs re- main un- changed.) &1 Note For CJPN(511), the ON/OFF status of CIO 000000 would be reversed. 3-5-6 MULTIPLE JUMP and JUMP END: JMP0(515) and JME0(516) Purpose When the execution condition for JMP0(515) is OFF, all instructions from JMP0(515) to the next JME0(516) in the program are processed as...
Page 221 Sequence Control Instructions Section 3-5 Description When the execution condition for JMP0(515) is ON, no jump is made and the program executed consecutively as written. When the execution condition for JMP0(515) is OFF, all instructions from JMP0(515) to the next JME0(516) in the program are processed as NOP(000).
Page 222 Sequence Control Instructions Section 3-5 CIO 000000 CIO 000000 Instructions processed Normal execution NOP(000). (Outputs re- main un- changed.) 3-5-7 FOR-NEXT LOOPS: FOR(512)/NEXT(513) Purpose The instructions between FOR(512) and NEXT(513) are repeated a specified number of times. FOR(512) and NEXT(513) are used in pairs. Ladder Symbols FOR(512) N: Number of loops...
Page 223 Sequence Control Instructions Section 3-5 Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank...
Page 224 Sequence Control Instructions Section 3-5 &3 &2 Use BREAK(514) to escape from a FOR-NEXT loop. Several BREAK(514) instructions (the number of levels nested) are required to escape from nested loops. The remaining instructions in the loop after BREAK(514) are processed as NOP(000) instructions.
Page 225 Sequence Control Instructions Section 3-5 Flags Name Label Operation Error Flag ON if more than 15 loops are nested. OFF in all other cases. Equals Flag Negative Flag Precautions Program FOR(512) and NEXT(513) in the same task. Execution will not be repeated if these instructions aren’t in the same task.
Page 226: Timer And Counter Instructions
Timer and Counter Instructions Section 3-6 Description Program BREAK(514) between FOR(512) and NEXT(513) to cancel the FOR-NEXT loop when BREAK(514) is executed. When BREAK(514) is exe- cuted, the rest of the instructions up to NEXT(513) are processed as NOP(000). Condition a ON N repetitions Repetitions forced to end.
Page 227 Timer and Counter Instructions Section 3-6 memory word). (That is, the contents of the addressed word is taken as either BCD or binary data according to the refresh method that is set.) Refer to the CS/CJ Series Programming Manual for details on refresh meth- ods.
Page 228 Timer and Counter Instructions Section 3-6 Item TIM/TIMX(550) TIMH(015)/ TMHH(540)/ TTIM(087)/ TIML(542)/ MTIM(543)/ TIMHX(551) TMHHX(552) TTIMX(555) TIMLX(553) MTIMX(554) Value Comp. after flags reset Note 1. TIM PVs are refreshed at execution, at the end of program execution each cycle, or every 80 ms by interrupt if the cycle time exceeds 80 ms. 2.
Page 229 Timer and Counter Instructions Section 3-6 Variations Variations Executed Each Cycle for ON Condition TIM/TIMX(550) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks...
Page 230 Timer and Counter Instructions Section 3-6 Description When the timer input is OFF, the timer specified by N is reset, i.e., the timer’s PV is reset to the SV and its Completion Flag is turned OFF. When the timer input goes from OFF to ON, TIM/TIMX(550) starts decrement- ing the PV.
Page 231 Timer and Counter Instructions Section 3-6 Timers will be reset or paused in the following cases. (When a timer is reset, its PV is reset to the SV and its Completion Flag is turned OFF.) Condition Completion Flag Operating mode changed from RUN or 0000 MONITOR mode to PROGRAM mode or vice versa.
Page 232 Section 3-6 Timer and Counter Instructions Timers Created with Timer Numbers 0000 to 2047 Execution of TIM/ The PV is updated every time that TIM/TIMX(550) is exe- TIMX(550) cuted. The Completion Flag is turned ON if the PV is 0000. The Completion Flag is turned OFF if the PV isn’t 0000.
Page 233 Section 3-6 Timer and Counter Instructions Ladder Symbol Symbol Operands refresh method N: 0000 to 4095 (decimal) TIMH(015) S: #0000 to #9999 (BCD) N: Timer number S: Set value Binary N: 00000 to 4095 (decimal) TIMHX(551) S: &0 to &65535 (decimal) #0000 to #FFFF (hex) N: Timer number S: Set value...
Page 234 Timer and Counter Instructions Section 3-6 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants BCD: #0000 to 9999 (BCD) “&” cannot be used. Binary: &0 to &65535 (decimal) #0000 to #FFFF (hex) Data Registers DR0 to DR15...
Page 235 Section 3-6 Timer and Counter Instructions Flags Name Label Operation Error Flag ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer. ON if in BCD mode and S does not contain BCD data. OFF in all other cases.
Page 236 Timer and Counter Instructions Section 3-6 2. If the IOM Hold Bit (A50012) has been turned ON and the status of the IOM Hold Bit itself is protected in the PLC Setup, the status of timer Completion Flags and PVs will be maintained even when the power is interrupted. 3.
Page 237 Timer and Counter Instructions Section 3-6 Example When timer input CIO 000000 goes from OFF to ON in the following example, the timer PV will begin counting down from the SV (#0064 = 100 = 1.00 s). The Timer Completion Flag, T0000, will be turned ON when the PV reaches 0000.
Page 238 Section 3-6 Timer and Counter Instructions Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959 Timer Area 0000 to 0015 (decimal) T0000 to T4095 Counter Area C0000 to C4095 DM Area...
Page 239 Timer and Counter Instructions Section 3-6 Note In CS1 and CJ1 CPU Units, these are turned OFF. In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left unchanged. Precautions Timer numbers are shared by the TIM, TIMX(550), TIMH(015), TIMHX(551), TMHH(540), TMHHX(552), TTIM(087), TTIMX(555), TIMW(813), TIMWX(816), TMHW(815), and TMHWX(817) instructions.
Page 240 Timer and Counter Instructions Section 3-6 The operation of the = Flag and N Flag depends on the model of the CPU Unit. Refer to Flags, above, for details. If online editing is used to convert a timer to another kind of timer with the same timer number (such as TMHH(540)/TMHHX(552) ↔...
Page 241 Timer and Counter Instructions Section 3-6 Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959 Timer Area 0000 to 4095 (decimal) T0000 to T4095 Counter Area C0000 to C4095 DM Area...
Page 242 Section 3-6 Timer and Counter Instructions Flags Name Label Operation Error Flag ON if N is indirectly addressed through an Index Register but the address in the Index Register is not the PV address of a timer. ON if in BCD mode and S does not contain BCD data. OFF in all other cases.
Page 243 Section 3-6 Timer and Counter Instructions The timer’s Completion Flag is refreshed only when TTIM(087)/TTIMX(555) is executed, so a delay of up to one cycle may be required for the Completion Flag to be turned ON after the timer times out. Typical timers such as TIM/TIMX(550) are decrementing counters and the PV shows the time remaining until the timer times out.
Page 244 Timer and Counter Instructions Section 3-6 Binary TIMLX(543) D1: Completion Flag D2: PV word S: SV word Variations Variations Executed Each Cycle for ON Condition TIML(542)/ TIMLX(553) Executed Once for Upward Differentiation Not supported. Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported.
Page 245 Section 3-6 Timer and Counter Instructions Area EM Area with bank En_00000 to En_00000 to En_32766 En_32767 (n = 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM...
Page 246 Timer and Counter Instructions Section 3-6 Precautions Unlike most timers, TIML(542)/TIMLX(553) does not use a timer number. (Timer area PV refreshing is not performed for TIML(542)/TIMLX(553).) Since the Completion Flag for TIML(542)/TIMLX(553) is in a data area it can be forced set or forced reset like other bits, but the PV will not change. The timer’s PV is refreshed only when TIML(542)/TIMLX(553) is executed, so the timer will not operate properly when the cycle time exceeds 100 ms because the timer increments in 100-ms units.
Page 247 Timer and Counter Instructions Section 3-6 3-6-6 MULTI-OUTPUT TIMER: MTIM(543)/MTIMX(554) Purpose MTIM(543)/MTIMX(554) operates a 0.1-s incrementing timer with eight inde- pendent SVs and Completion Flags. The set value is 0 to 999.9 s for MTIM(543) and 0 to 6,553.5 s for MTIMX(554), and the timer accuracy is 0 to 0.01 s.
Page 248 Section 3-6 Timer and Counter Instructions S: First SV Word S through S+7 contain the eight independent SVs. Each SV must be as follows: Data Range #0000 to #9999 Binary &0 to &65535 (decimal) #0000 to #FFFF (hex) Corresponding bit (Completion Flag) in D1 Data Range...
Page 249 Timer and Counter Instructions Section 3-6 Area Index Registers Indirect addressing using ,IR0 to ,IR15 Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description When the execution condition for MTIM(543)/MTIMX(554) is ON and the reset and timer bits are both OFF, MTIM(543)/MTIMX(554) increments the PV in...
Page 250 Timer and Counter Instructions Section 3-6 Reset bit Pause bit Operation (Bit 08) (Bit 09) The PV will be reset to 0000 and the Completion Flags will be turned OFF. The PV will not be updated. The reset and pause bits are effective only when the execution condition for MTIM(543)/MTIMX(554) is ON.
Page 251 Timer and Counter Instructions Section 3-6 Example When CIO 000000 is ON and the pause bit (CIO 010009) is OFF in the follow- ing example, the timer will start operating when the reset bit (CIO 010009) is turned from ON to OFF. The timer’s PV will begin timing up from 0000. The eight SVs in D00200 through D00207 are compared to the PV and the corresponding Completion Flags (CIO 010000 through CIO 010007) are turned on when the SV ≤...
Page 252 Timer and Counter Instructions Section 3-6 3-6-7 COUNTER: CNT/CNTX(546) Purpose CNT/CNTX(546) operates a decrementing counter. The setting range 0 to 9,999 for CNT and 0 to 65,535 for CNTX(546). Ladder Symbol Count input N: Counter number S: Set value Reset input Binary Count input CNTX(546)
Page 253 Timer and Counter Instructions Section 3-6 Area Indirect DM/EM @ D00000 to @ D32767 addresses in @ E00000 to @ E32767 binary @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 254 Timer and Counter Instructions Section 3-6 Precautions Counter numbers are shared by the CNT, CNTX(546), CNTR(012), CNTRX(548), CNTW(814), and CNTWX(818) instructions. If two counters share the same counter number but are not used simultaneously, a duplica- tion error will be generated when the program is checked but the counters will operate normally.
Page 255 Timer and Counter Instructions Section 3-6 First Cycle Flag (A20011) 3-6-8 REVERSIBLE COUNTER: CNTR(012)/CNTRX(548) Purpose CNTR(012)/CNTRX(548) operates a reversible counter. Ladder Symbol Increment input CNTR(012) N: Counter number S: Set value Decrement input Reset input Binary Increment input CNTRX(548) N: Counter number S: Set value Decrement input Reset input...
Page 256 Timer and Counter Instructions Section 3-6 Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area --- H000 to H511 Auxiliary Bit A000 to A959 Area Timer Area T0000 to T4095 Counter Area 0000 to 4095 (decimal) C0000 to C4095 DM Area...
Page 257 Timer and Counter Instructions Section 3-6 Counter PV Completion Flag When decrementing, the Completion Flag will be turned ON when the PV is decremented from 0 up to the SV and it will be turned OFF again when the PV is decremented from the SV to SV –...
Page 258 Timer and Counter Instructions Section 3-6 Increment input Decrement input Increment input Reset input CIO 000000 Decrement input CIO 000001 Reset input CIO 000002 Counter PV C0001 Completion Flag C0001 Specifying the SV in a Word In the following example, the SV for CNTR(012) 0007 is determined by the content of CIO 0001.
Page 259 Timer and Counter Instructions Section 3-6 3-6-9 RESET TIMER/COUNTER: CNR(545)/CNRX(547) Purpose Resets the timers or counters within the specified range of timer or counter numbers. Ladder Symbol CNR(545) : First number in range : Last number in range Binary CNRX(547) : First number in range : Last number in range Variations...
Page 260 Timer and Counter Instructions Section 3-6 Area Constants Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description CNR(545)/CNRX(547) resets the Completion Flags of all timers or counters from N...
Page 261 Timer and Counter Instructions Section 3-6 When CIO 000001 is ON, the Completion Flags for counters C0003 to C0007 are turned OFF and the counters’ PVs are set to the maximum value of 9999. 3-6-10 Example Timer and Counter Applications The following examples show various applications of timer and counter instructions including long-term timers, a two-stage counter, ON/OFF delay, one-shot bit, and flicker bit.
Page 262 Section 3-6 Timer and Counter Instructions Address Instruction Operands 000000 010000 000001 000001 000002 0002 #0100 000003 000000 000004 AND NOT 010000 Start Count up 000005 AND NOT C0002 000006 0001 #0050 000007 T0001 000008 010000 000009 C0002 000010 000201 Clock Pulse and CNT Instruction In this example, a CNT instruction counts the pulses from the 1-s clock pulse to make a 700-second timer.
Page 263 Section 3-6 Timer and Counter Instructions Example 3: In this example two TIM timers are combined with KEEP(011) to make an ON ON/OFF Delay delay and an OFF delay. CIO 000500 will be turned ON 5.0 seconds after CIO 000000 goes ON and it will be turned OFF 3.0 seconds after CIO 000000 goes OFF.
Page 264 Timer and Counter Instructions Section 3-6 Example 4: The following program examples show two ways to create flicker bits. The second example just mimics a clock pulse. Flicker Bit Two TIM Instructions Two TIM timers can be combined to make a bit turn ON and OFF at regular intervals while the execution condition is ON.
Page 265 Section 3-6 Timer and Counter Instructions The timer or counter instruction won’t be executed if the PLC memory address in the specified Index Register is not the address of a timer or counter PV. Using Index Registers to indirectly address timers and counters can reduce the size of the program and increase flexibility.
Page 266 Timer and Counter Instructions Section 3-6 2. MOVR(560) moves the PLC memory address of the Completion Flag for timer T0000 to IR1. 3. MOVR(560) moves the PLC memory address of CIO 200000 into IR2. 4. MOV(021) moves &100 into D00000 for indirect addressing of the timer SVs.
Page 267: Comparison Instructions
Comparison Instructions Section 3-7 Comparison Instructions This section describes instructions used to compare data of various lengths and in various ways. Instruction Mnemonic Function code Page Input Comparison Instructions LD, AND, OR 300 to 328 =, <>, <, <=, >, >=, L, S COMPARE DOUBLE COMPARE CMPL...
Page 268 Section 3-7 Comparison Instructions Area EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_ 32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD...
Page 269 Comparison Instructions Section 3-7 Description The input comparison instruction compares S and S as signed or unsigned values and creates an ON execution condition when the comparison condition is true. Unlike instructions such as CMP(020) and CMPL(060), the result of an input comparison instruction is reflected directly as an execution condition, so it isn’t necessary to access the result of the comparison through an Arithmetic Flag and the program is simpler and faster.
Page 270 Comparison Instructions Section 3-7 Summary of Input Comparison Instructions The following table shows the function codes, mnemonics, names, and func- tions of the 72 input comparison instructions. (For one-word comparisons C1=S and C2=S ; for double comparisons C1=S +1, S and C2=S +1, S Code Mnemonic...
Page 271 Comparison Instructions Section 3-7 Code Mnemonic Name Function LD<=SL LOAD DOUBLE SIGNED LESS THAN OR EQUAL True if C1 ≤ C2 AND<=SL AND DOUBLE SIGNED LESS THAN OR EQUAL OR<=SL OR DOUBLE SIGNED LESS THAN OR EQUAL LD> LOAD GREATER THAN True if C1 >...
Page 272 Comparison Instructions Section 3-7 Name Label Operation ≤ S Less Than or < = ON if S with one-word data. Equal Flag ≤ S ON if S +1, S +1, S with double-length data. OFF in all other cases. Negative Flag OFF or unchanged (See note.) Note In CS1 and CJ1 CPU Units, these Flags are turned OFF.
Page 273 Comparison Instructions Section 3-7 3-7-2 COMPARE: CMP(020) Purpose Compares two unsigned binary values (constants and/or the contents of specified words) and outputs the result to the Arithmetic Flags in the Auxiliary Area. Ladder Symbol CMP(020) : Comparison data 1 : Comparison data 2 Variations Variations Executed Each Cycle for ON Condition...
Page 274 Comparison Instructions Section 3-7 Description CMP(020) compares the unsigned binary data in S and S and outputs the result to Arithmetic Flags (the Greater Than, Greater Than or Equal, Equal, Less Than or Equal, Less Than, and Not Equal Flags) in the Auxiliary Area. Unsigned binary comparison Arithmetic Flags...
Page 275 Comparison Instructions Section 3-7 The immediate-refreshing variation (!CMP(020)) can be used with words allo- cated to external inputs specified in S and/or S . When !CMP(020) is exe- cuted, input refreshing will be performed for the external input word specified in S and/or S and that refreshed value will be compared.
Page 276 Comparison Instructions Section 3-7 Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area D00000 to D32766 EM Area without bank...
Page 277 Comparison Instructions Section 3-7 Using CMPL(060) Results in the Program When CMPL(060) is executed, the result is reflected in the Arithmetic Flags. Control the desired output or right-hand instruction with a branch from the same input condition that controls CMPL(060), as shown in the following dia- gram.
Page 278 Comparison Instructions Section 3-7 Note In CS1 and CJ1 CPU Units, these Flags are turned OFF. In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left unchanged. Precautions Do not program another instruction between CMPL(060) and an input condi- tion that accesses the result of CMPL(060) because the other instruction might change the status of the Arithmetic Flags.
Page 279 Comparison Instructions Section 3-7 Area Auxiliary Bit Area A000 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767...
Page 280 Comparison Instructions Section 3-7 gram. In this case, the Equals Flag and output A will be turned ON when S Correct Use of CPS(114) Arithmetic Flag (Example: Equal Flag) Using CPS(114) Results in the Program Do not program another instruction between CPS(114) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag.
Page 281 Comparison Instructions Section 3-7 Note In CS1 and CJ1 CPU Units, these Flags are turned OFF. In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left unchanged. Precautions Do not program another instruction between CPS(114) and an input condition that accesses the result of CPS(114) because the other instruction might change the status of the Arithmetic Flags.
Page 282 Comparison Instructions Section 3-7 Area Index Registers Indirect addressing using ,IR0 to ,IR15 Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description CPSL(115) compares the double signed binary data in S +1, S and S and outputs the result to Arithmetic Flags (the Greater Than, Greater Than...
Page 283 Comparison Instructions Section 3-7 the status of the Arithmetic Flag. In this case, the results of instruction B might change the results of CPSL(115). Incorrect Use of CPSL(115) CPSL Instruction Arithmetic Flag (Example: Equal Flag) Flags Name Label Operation Error Flag OFF or unchanged (See note.) Greater Than Flag >...
Page 284 Comparison Instructions Section 3-7 Flag status 1234 5678 > D0001 Comparison D0005 < ABCD EF12 3-7-6 MULTIPLE COMPARE: MCMP(019) Purpose Compares 16 consecutive words with another 16 consecutive words and turns ON the corresponding bit in the result word where the contents of the words are not equal.
Page 285 Comparison Instructions Section 3-7 Operand Specifications Area CIO Area CIO 0000 to CIO 6128 CIO 0000 to CIO 6143 Work Area W000 to W496 W000 to W511 Holding Bit Area H000 to H496 H000 to H511 Auxiliary Bit Area A000 to A944 A448 to A959 Timer Area T0000 to T4080...
Page 286 Comparison Instructions Section 3-7 Flags Name Label Operation Error Flag Equals Flag ON if the result word is 0000. (The two 16-word sets contain the same data.) OFF in all other cases. Example When CIO 000000 is ON in the following example, MCMP(019) compares words D00100 through D00115 in order to words D00200 through D00215 and turns ON the corresponding bits in D00300 when the words are not equal.
Page 287 Comparison Instructions Section 3-7 Operands T: First word of table Specifies the beginning of the 16-word table. T and T+15 must be in the same data area. R: Result word Each bit of R contains the result of a comparison between S and a word in the 16-word table.
Page 288 Comparison Instructions Section 3-7 Description TCMP(085) compares the source data (S) to each of the 16 words T through T+15 and turns ON the corresponding bit in word R when the data are equal. Bit n of R is turned ON if the content of T+n is equal to S and it is turned OFF if they are not equal.
Page 289 Comparison Instructions Section 3-7 3-7-8 BLOCK COMPARE: BCMP(068) Purpose Compares the source data to 16 ranges (defined by 16 lower limits and 16 upper limits) and turns ON the corresponding bit in the result word when the source data is within a range. Ladder Symbol BCMP(068) S: Source data...
Page 290 Comparison Instructions Section 3-7 Area EM Area with bank En_00000 to En_00000 to En_00000 to En_32767 En_32736 En_32767 (n = 0 to C) (n = 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 291 Comparison Instructions Section 3-7 Flags Name Label Operation Error Flag Equals Flag ON if the result word is 0000. (S is not within any of the 16 ranges.) OFF in all other cases. Precautions An error will not occur if the lower limit is greater than the upper limit, but 0 (not within the range) will be output to the corresponding bit of R.
Page 292 Section 3-7 Comparison Instructions Variations Variations Executed Each Cycle for ON Condition BCMP2(502) Executed Once for Upward Differentiation @BCMP2(502) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 293 Section 3-7 Comparison Instructions Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959 A448 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767...
Page 294 Comparison Instructions Section 3-7 Setting Ranges The values A and B for each range will determine how the comparison oper- ates depending on which value is larger, as shown below. · If Value A ≤ Value B Then, Value A ≤ Comparison range ≤ Value B Comparison range Value A Value B...
Page 295 Section 3-7 Comparison Instructions D00203 and D00204, D00247 and D00248, and the other words in the com- parison block, and bit 1 in CIO 0100, bit 7 in CIO 1010, and the other bits in the result words are manipulated according to the results of comparison. 000000 0 0 1 7 R: CIO 0100...
Page 296 Comparison Instructions Section 3-7 Area EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD...
Page 297 Comparison Instructions Section 3-7 Correct Use of ZCP(088) Arithmetic Flag (Example: Equal Flag) Do not program another instruction between ZCP(088) and the instruction controlled by the Arithmetic Flag because the other instruction might change the status of the Arithmetic Flag. In this case, the results of instruction B might change the results of ZCP(088).
Page 298 Section 3-7 Comparison Instructions Arithmetic 000000 Flags D00000 D00000 0005Hex ≤ ≤ 001FHex ON(1) #0005 D00000 #001F > 001FHex > ON(1) D00000 002000 0005Hex > < ON(1) 002001 > 002002 < 3-7-11 DOUBLE AREA RANGE COMPARE: ZCPL(116) Purpose Compares a 32-bit unsigned binary value (CD+1, CD) with the range defined by lower limit (LL+1, LL) and upper limit (UL+1, UL).
Page 299 Comparison Instructions Section 3-7 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 300: Data Movement Instructions
Data Movement Instructions Section 3-8 Name Label Operation Greater Than or Equal Flag > = Left unchanged. ON if LL+1, LL ≤ CD+1, CD ≤ UL+1, UL. Equal Flag OFF in all other cases. Not Equal Flag <> Left unchanged. Less Than Flag <...
Page 301 Data Movement Instructions Section 3-8 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 302 Data Movement Instructions Section 3-8 3-8-2 MOVE NOT: MVN(022) Purpose Transfers the complement of a word of data to the specified word. Ladder Symbol MVN(022) S: Source D: Destination Variations Variations Executed Each Cycle for ON Condition MVN(022) Executed Once for Upward Differentiation @MVN(022) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 303 Data Movement Instructions Section 3-8 Description MVN(022) inverts the bits in S and transfers the result to D. The content of S is left unchanged. Source word Destination word Bit status inverted. Flags Name Label Operation Error Flag Equals Flag ON if the content of D is 0000 after execution.
Page 304 Data Movement Instructions Section 3-8 Area Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 A448 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area D00000 to D32766 EM Area without bank E00000 to E32766 EM Area with bank En_00000 to En_32766...
Page 305 Data Movement Instructions Section 3-8 Example When CIO 000000 is ON in the following example, the content of D00101 and D00100 are copied to D00201 and D00200. 3-8-4 DOUBLE MOVE NOT: MVNL(499) Purpose Transfers the complement of two words of data to the specified words. Ladder Symbol MVNL(499) S: First source word...
Page 306 Data Movement Instructions Section 3-8 Area Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –) IR0 to, –(– –) IR15 Description MVNL(499) inverts the bits in S+1 and S and transfers the result to D+1 and D.
Page 307 Data Movement Instructions Section 3-8 Variations Variations Executed Each Cycle for ON Condition MOVB(082) Executed Once for Upward Differentiation @MOVB(082) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 308 Data Movement Instructions Section 3-8 Description MOVB(082) copies the specified bit (n) from S to the specified bit (m) in D. The other bits in the destination word are left unchanged. Note The same word can be specified for both S and D to copy a bit within a word. Flags Name Label...
Page 309 Data Movement Instructions Section 3-8 Operands S: Source Word The source digits are read from right to left, wrapping back to the rightmost digit (digit 0) if necessary. Digit 3 Digit 2 Digit 1 Digit 0 C: Control Word The first three digits of C indicate the first source digit (m), the number of dig- its to transfer (n), and the first destination digit (l), as shown in the following diagram.
Page 310 Data Movement Instructions Section 3-8 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –) IR0 to, –(– –) IR15 Description MOVD(083) copies the content of n digits from S (beginning at digit m) to D (beginning at digit l).
Page 311 Data Movement Instructions Section 3-8 Examples of C The following diagram shows examples of data transfers for various values of Digit 0 Digit 0 Digit 0 Digit 0 Digit 0 Digit 0 Digit 0 Digit 0 Digit 1 Digit 1 Digit 1 Digit 1 Digit 1...
Page 312 Data Movement Instructions Section 3-8 D: First Destination Word Specifies the first destination word. Bits are written from right to left, continu- ing with consecutive words (up to D+16) when necessary. D+16 max. Note The destination words must be in the same data area. Operand Specifications Area CIO Area...
Page 313 Data Movement Instructions Section 3-8 It is possible for the source words and destination words to overlap. By trans- ferring data overlapping several words, the data can be packed more effi- ciently in the data area. (This is particularly useful when handling position data for position control.) Since the source words and destination words can overlap, XFRB(062) can be combined with ANDW(034) to shift m bits by n spaces.
Page 314 Data Movement Instructions Section 3-8 Variations Variations Executed Each Cycle for ON Condition XFER(070) Executed Once for Upward Differentiation @XFER(070) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 315 Data Movement Instructions Section 3-8 Area Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –) IR0 to, –(– –) IR15 Description XFER(070) copies N words beginning with S (S to S+(N–1)) to the N words beginning with D (D to D+(N–1)).
Page 316 Data Movement Instructions Section 3-8 3-8-9 BLOCK SET: BSET(071) Purpose Copies the same word to a range of consecutive words. Ladder Symbol BSET(071) S: Source word St: Starting word E: End word Variations Variations Executed Each Cycle for ON Condition BSET(071) Executed Once for Upward Differentiation @BSET(071)
Page 317 Data Movement Instructions Section 3-8 Area EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM...
Page 318 Data Movement Instructions Section 3-8 3-8-10 DATA EXCHANGE: XCHG(073) Purpose Exchanges the contents of the two specified words. Ladder Symbol XCHG(073) E1: First exchange word E2: Second exchange word Variations Variations Executed Each Cycle for ON Condition XCHG(073) Executed Once for Upward Differentiation @XCHG(073) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 319 Data Movement Instructions Section 3-8 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++)
Page 320 Data Movement Instructions Section 3-8 Variations Variations Executed Each Cycle for ON Condition XCGL(562) Executed Once for Upward Differentiation @XCGL(562) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications...
Page 321 Data Movement Instructions Section 3-8 XFER(070) operation Buffer XFER(070) operation XFER(070) operation Flags Name Label Operation Error Flag OFF or unchanged (See note.) Equals Flag OFF or unchanged (See note.) Negative Flag OFF or unchanged (See note.) Note In CS1 and CJ1 CPU Units, these Flags are turned OFF. In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left unchanged.
Page 322 Data Movement Instructions Section 3-8 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands Bs: Destination Base Address Specifies the destination base address. The offset is added to this address to calculate the destination word. Of: Offset This value is added to the base address to calculate the destination word.
Page 323 Data Movement Instructions Section 3-8 Description DIST(080) copies S to the destination word calculated by adding Of to Bs. The same DIST(080) instruction can be used to distribute the source word to various words in the data area by changing the value of Of. Bs+n Flags Name...
Page 324 Data Movement Instructions Section 3-8 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands Bs: Source Base Address Specifies the source base address. The offset is added to this address to cal- culate the source word. Of: Offset This value is added to the base address to calculate the source word.
Page 325 Data Movement Instructions Section 3-8 Description COLL(081) copies the source word (calculated by adding Of to Bs) to the des- tination word. The same COLL(081) instruction can be used to collect data from various source words in the data area by changing the value of Of. Bs+n Flags Name...
Page 326 Data Movement Instructions Section 3-8 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands D: Destination The destination must be an Index Register (IR0 to IR15). Operand Specifications Area CIO Area CIO 0000 to CIO 6143 CIO 000000 to CIO 614315 Work Area W000 to W511...
Page 327 Data Movement Instructions Section 3-8 Flags Name Label Operation Error Flag OFF or unchanged (See note.) Equals Flag OFF or unchanged (See note.) Negative Flag OFF or unchanged (See note.) Note In CS1 and CJ1 CPU Units, these Flags are turned OFF. In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, these Flags are left unchanged.
Page 328 Data Movement Instructions Section 3-8 Operand Specifications Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area T0000 to T4095 (present value) Counter Area C0000 to C4095 (present value) DM Area EM Area without bank EM Area with bank Indirect DM/EM addresses in binary Indirect DM/EM...
Page 329: Data Shift Instructions
Data Shift Instructions Section 3-9 Example When CIO 000000 is ON in the following example, MOVRW(561) writes the PLC memory address for the PV of timer T0000 to IR1. Internal I/O memory address Data Shift Instructions This section describes instructions used to shift data within or between words, but in differing amounts and directions.
Page 330 Data Shift Instructions Section 3-9 3-9-1 SHIFT REGISTER: SFT(010) Purpose Operates a shift register. Ladder Symbol Data input SFT(010) Shift input St: Starting word Reset input E: End word Variations Variations Executed Each Cycle for ON Condition SFT(010) Executed Once for Upward Differentiation Not supported Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 331 Data Shift Instructions Section 3-9 Description When the execution condition on the shift input changes from OFF to ON, all the data from St to E is shifted to the left by one bit (from the rightmost bit to the leftmost bit), and the ON/OFF status of the data input is placed in the rightmost bit.
Page 332 Data Shift Instructions Section 3-9 Variations Variations Executed Each Cycle for ON Condition SFTR(084) Executed Once for Upward Differentiation @SFTR(084) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 333 Data Shift Instructions Section 3-9 Description When the execution condition of the shift input bit (bit 14 of C) changes to ON, all the data from St to E is moved in the designated shift direction (designated by bit 12 of C) by 1 bit, and the ON/OFF status of the data input is placed in the rightmost or leftmost bit.
Page 334 Data Shift Instructions Section 3-9 Controlling Data Resetting Data All bits from St to E and the Carry Flag are set to 0 and no other data can be received when the reset input bit (bit 15 of C) is ON. Shifting Data Left (from Rightmost to Leftmost Bit) When the shift input bit (bit 14 of C) is ON, the contents of the input bit (bit 13 of C) is shifted to bit 00 of the starting word, and each bit thereafter is shifted...
Page 335 Data Shift Instructions Section 3-9 Operands C: Control Word 15 14 13 12 Shift direction 0: Non-zero data shifted toward E 1: Non-zero data shifted toward St Shift Enable Bit 0: Shift disabled 1: Shift enabled Clear Bit 0: Data not reset 1: All data from St to E is reset Note St and E must be in the same data area.
Page 336 Data Shift Instructions Section 3-9 Shift direction Shift enabled Convert . . . Clear Convert Non-zero data . . . Zero data Flags Name Label Operation Error Flag ON when St is greater than E. OFF in all other cases. Precautions When the Clear Flag (bit 15 of C) goes ON, all bits in the shift register, from St to E, will be reset (i.e., set to 0).
Page 337 Data Shift Instructions Section 3-9 3-9-4 WORD SHIFT: WSFT(016) Purpose Shifts data between St and E in word units. Ladder Symbol WSFT(016) S: Source word St: Starting word E: End word Variations Variations Executed Each Cycle for ON Condition WSFT(016) Executed Once for Upward Differentiation @WSFT(016) Executed Once for Downward Differentiation Not supported...
Page 338 Data Shift Instructions Section 3-9 Description WSFT(016) shifts data from St to E in word units and the data from the source word S is places into St. The contents of E is lost. Lost Flags Name Label Operation Error Flag ON when St is greater than E.
Page 339 Data Shift Instructions Section 3-9 Area Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 340 Data Shift Instructions Section 3-9 Examples When CIO 000000 is ON, CIO 0100 will be shifted one bit to the left. “0” will be placed in CIO 010000 and the contents of CIO 010115 will be shifted to the Carry Flag (CY). 3-9-6 DOUBLE SHIFT LEFT: ASLL(570) Purpose...
Page 341 Data Shift Instructions Section 3-9 Area Constants Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description ASLL(570) shifts the contents of Wd and Wd +1 one bit to the left (from right- most bit to leftmost bit).
Page 342 Data Shift Instructions Section 3-9 3-9-7 ARITHMETIC SHIFT RIGHT: ASR(026) Purpose Shifts the contents of Wd one bit to the right. Ladder Symbol ASR(026) Wd: Word Variations Variations Executed Each Cycle for ON Condition ASR(026) Executed Once for Upward Differentiation @ASR(026) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 343 Data Shift Instructions Section 3-9 Description ASR(026) shifts the contents of Wd one bit to the right (from leftmost bit to rightmost bit). “0” will be placed in the leftmost bit and the contents of the rightmost bit will be shifted into the Carry Flag (CY). Flags Name Label...
Page 344 Data Shift Instructions Section 3-9 Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A448 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area D00000 to D32766 EM Area without bank...
Page 345 Data Shift Instructions Section 3-9 Examples When CIO 000000 is ON, word CIO 0100 and CIO 0101 will shift one bit to the right. “0” will be placed into CIO 010115 and the contents of CIO 010000 will be shifted to the Carry Flag (CY). 3-9-9 ROTATE LEFT: ROL(027) Purpose...
Page 346 Data Shift Instructions Section 3-9 Area Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description ROL(027) shifts all bits of Wd including the Carry Flag (CY) to the left (from rightmost bit to leftmost bit).
Page 347 Data Shift Instructions Section 3-9 3-9-10 DOUBLE ROTATE LEFT: ROLL(572) Purpose Shifts all Wd and Wd +1 bits one bit to the left including the Carry Flag (CY). Ladder Symbol ROLL(572) Wd: Word Variations Variations Executed Each Cycle for ON Condition ROLL(572) Executed Once for Upward Differentiation @ROLL(572)
Page 348 Data Shift Instructions Section 3-9 Flags Name Label Operation Error Flag Equals Flag ON when the shift result is 0. OFF in all other cases. Carry Flag ON when 1 is shifted into the Carry Flag (CY). OFF in all other cases. Negative Flag ON when the leftmost bit is 1 as a result of the shift.
Page 349 Data Shift Instructions Section 3-9 Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A448 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank...
Page 350 Data Shift Instructions Section 3-9 Note It is possible to set the Carry Flag contents to 1 or 0 immediately before exe- cuting this instruction, by using the Set Carry (STC(040)) or Clear Carry (CLC(041)) instructions. Examples When CIO 000000 is ON, word CIO 0100 and the Carry Flag (CY) will shift one bit to the right.
Page 351 Data Shift Instructions Section 3-9 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0++) to ,IR15+(++) ,–(–...
Page 352 Data Shift Instructions Section 3-9 3-9-13 ROTATE LEFT WITHOUT CARRY: RLNC(574) Purpose Shifts all Wd bits one bit to the left not including the Carry Flag (CY). Ladder Symbol RLNC(574) Wd: Word Variations Variations Executed Each Cycle for ON Condition RLNC(574) Executed Once for Upward Differentiation @RLNC(574)
Page 353 Data Shift Instructions Section 3-9 Description RLNC(574) shifts all bits of Wd to the left (from rightmost bit to leftmost bit). The contents of the leftmost bit of Wd shifts to the rightmost bit and to the Carry Flag (CY). Flags Name Label...
Page 354 Data Shift Instructions Section 3-9 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A448 to A958 Timer Area T0000 to T4094...
Page 355 Data Shift Instructions Section 3-9 Precautions When RLNL(576) is executed, the Error Flag will turn OFF. If as a result of the shift the contents of Wd and Wd +1 are zero, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of Wd + 1 is 1, the Neg- ative Flag will turn ON.
Page 356 Data Shift Instructions Section 3-9 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 357 Data Shift Instructions Section 3-9 Examples When CIO 000000 is ON, word CIO 0100 will shift one bit to the right (exclud- ing the Carry Flag (CY)). The contents of CIO 010000 will be shifted to CIO 010015. Wd: CIO 0100 Instruction executed once 3-9-16 DOUBLE ROTATE RIGHT WITHOUT CARRY: RRNL(577) Purpose...
Page 358 Data Shift Instructions Section 3-9 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 359 Data Shift Instructions Section 3-9 3-9-17 ONE DIGIT SHIFT LEFT: SLD(074) Purpose Shifts data by one digit (4 bits) to the left. Ladder Symbol SLD(074) St: Starting word E: End word Variations Variations Executed Each Cycle for ON Condition SLD(074) Executed Once for Upward Differentiation @SLD(074) Executed Once for Downward Differentiation Not supported...
Page 360 Data Shift Instructions Section 3-9 Description SLD(074) shifts data between St and E by one digit (4 bits) to the left. “0” is placed in the rightmost digit (bits 3 to 0 of St), and the content of the leftmost digit (bits 15 to 12 of E) is lost.
Page 361 Data Shift Instructions Section 3-9 Area Auxiliary Bit Area A448 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767...
Page 362 Data Shift Instructions Section 3-9 Examples When CIO 000000 is ON, words CIO 0100 through CIO 0102 will shift by one digit (4 bits) to the right. A zero will be placed in bits 12 to 15 of CIO 0102 and the contents of bits 0 to 3 of word CIO 0100 will be lost.
Page 363 Data Shift Instructions Section 3-9 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants #0000 to #000F #0000 to #FFFF (binary) or &0 to (binary) or &0 to &15 &65535 Data Registers...
Page 364 Data Shift Instructions Section 3-9 &3 &11 C: Starting from bit 3 N: 11 bits D: CIO 0100 D: CIO 0100 3-9-20 SHIFT N-BIT DATA RIGHT: NSFR(579) Purpose Shifts the specified number of bits to the right. Ladder Symbol NSFR(579) D: Beginning word for shift C: Beginning bit N: Shift data length...
Page 365 Data Shift Instructions Section 3-9 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 366 Data Shift Instructions Section 3-9 &2 &11 C: Starting from bit 2 N: 11 bits 3-9-21 SHIFT N-BITS LEFT: NASL(580) Purpose Shifts the specified 16 bits of word data to the left by the specified number of bits. Ladder Symbol NASL(580) D: Shift word C: Control word...
Page 367 Data Shift Instructions Section 3-9 Area Auxiliary Bit Area A448 to A959 A000 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM...
Page 368 Data Shift Instructions Section 3-9 Precautions For any bits which are shifted outside the specified word, the contents of the last bit is shifted to the Carry Flag (CY), and all other data is lost. When the number of bits to shift (specified in C) is “0,” the data will not be shifted.
Page 369 Data Shift Instructions Section 3-9 3-9-22 DOUBLE SHIFT N-BITS LEFT: NSLL(582) Purpose Shifts the specified 32 bits of word data to the left by the specified number of bits. Ladder Symbol NSLL(582) D: Shift word C: Control word Variations Variations Executed Each Cycle for ON Condition NSLL(582) Executed Once for Upward Differentiation...
Page 370 Data Shift Instructions Section 3-9 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Specified values only Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15...
Page 371 Data Shift Instructions Section 3-9 is specified in bits 0 to 7 of word CIO 0300 (control data). The contents of bit 0 of CIO 0100 is copied into bits from which data was shifted and the contents of the rightmost bit which was shifted out of range is shifted into the Carry Flag (CY).
Page 372 Data Shift Instructions Section 3-9 Operands C: Control Word No. of bits to shift: 00 to 10 Hex Always 0. Data shifted into register 0 Hex: 0 shifted in 8 Hex: Contents of rightmost bit shifted in Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area...
Page 373 Data Shift Instructions Section 3-9 zeros or the value of the rightmost bit will be placed into the specified number of bits of the shift word starting from the rightmost bit. Contents of "a" or "0" shifted in Lost N bits Flags Name Label...
Page 374 Data Shift Instructions Section 3-9 Leftmost bit Lost No. of bits to shift: 10 bits (Contents of the leftmost bit is inserted.) 3-9-24 DOUBLE SHIFT N-BITS RIGHT: NSRL(583) Purpose Shifts the specified 32 bits of word data to the right by the specified number of bits.
Page 375 Data Shift Instructions Section 3-9 Area EM Area without bank E00000 to E32766 E00000 to E32767 EM Area with bank En_00000 to En_32766 En_00000 to En_32767 (n = 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 376 Data Shift Instructions Section 3-9 If as a result of the shift the contents of D +1 is 00000000 Hex, the Equals Flag will turn ON. If as a result of the shift the contents of the leftmost bit of D +1 is 1, the Nega- tive Flag will turn ON.
Page 377: Increment/Decrement Instructions
Increment/Decrement Instructions Section 3-10 3-10 Increment/Decrement Instructions 3-10-1 INCREMENT BINARY: ++(590) Purpose Increments the 4-digit hexadecimal content of the specified word by 1. Ladder Symbol ++(590) Wd: Word Variations Variations Executed Each Cycle for ON Condition ++(590) Executed Once for Upward Differentiation @++(590) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 378 Increment/Decrement Instructions Section 3-10 (@++(590)) is used, the specified word is incremented only when the execu- tion condition has gone from OFF to ON. The Equals Flag will be turned ON if the result is 0000, the Carry Flag will be turned ON when a digit changes from F to 0, and the Negative Flag will be turned ON when bit 15 of Wd is ON in the result.
Page 379 Increment/Decrement Instructions Section 3-10 3-10-2 DOUBLE INCREMENT BINARY: ++L(591) Purpose Increments the 8-digit hexadecimal content of the specified words by 1. Ladder Symbol ++L(591) Wd: First word Variations Variations Executed Each Cycle for ON Condition ++L(591) Executed Once for Upward Differentiation @++L(591) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 380 Increment/Decrement Instructions Section 3-10 specified words is incremented only when the execution condition has gone from OFF to ON. Wd+1 Wd+1 The Equals Flag will be turned ON if the result is 0000 0000, the Carry Flag will be turned ON when a digit changes from F to 0, and the Negative Flag will be turned ON if bit 15 of Wd+1 is ON in the result.
Page 381 Increment/Decrement Instructions Section 3-10 3-10-3 DECREMENT BINARY: – –(592) Purpose Decrements the 4-digit hexadecimal content of the specified word by 1. Ladder Symbol − −(592) Wd: Word Variations Variations Executed Each Cycle for ON Condition – – (592) Executed Once for Upward Differentiation @–...
Page 382 Increment/Decrement Instructions Section 3-10 The Equals Flag will be turned ON if the result is 0000, the Carry Flag will be turned ON when a digit changes from 0 to F, and the Negative Flag will be turned ON if bit 15 of Wd is ON in the result. Both the Carry Flag and the Negative Flag will be turned ON when the content of Wd changes from 0000 to FFFF.
Page 383 Increment/Decrement Instructions Section 3-10 3-10-4 DOUBLE DECREMENT BINARY: – –L(593) Purpose Decrements the 8-digit hexadecimal content of the specified words by 1. Ladder Symbol − −L(593) Wd: First word Variations Variations Executed Each Cycle for ON Condition – –L(593) Executed Once for Upward Differentiation @–...
Page 384 Increment/Decrement Instructions Section 3-10 of the specified words is decremented only when the execution condition has gone from OFF to ON. Wd+1 Wd+1 The Equals Flag will be turned ON if the result is 0000 0000, the Carry Flag will be turned ON when a digit changes from 0 to F, and the Negative Flag will be turned ON if bit 15 of Wd+1 is ON in the result.
Page 385 Increment/Decrement Instructions Section 3-10 3-10-5 INCREMENT BCD: ++B(594) Purpose Increments the 4-digit BCD content of the specified word by 1. Ladder Symbol ++B(594) Wd: Word Variations Variations Executed Each Cycle for ON Condition ++B(594) Executed Once for Upward Differentiation @++B(594) Executed Once for Downward Not supported Differentiation...
Page 386 Increment/Decrement Instructions Section 3-10 The Equals Flag will be turned ON if the result is 0000 and the Carry Flag will be turned ON when a digit changes from 9 to 0. Both the Equals Flag and the Carry Flag will be turned ON when the content of Wd changes from 9999 to 0000.
Page 387 Increment/Decrement Instructions Section 3-10 3-10-6 DOUBLE INCREMENT BCD: ++BL(595) Purpose Increments the 8-digit BCD content of the specified words by 1. Ladder Symbol ++BL(595) Wd: First word Variations Variations Executed Each Cycle for ON Condition ++BL(595) Executed Once for Upward Differentiation @++BL(595) Executed Once for Downward Not supported...
Page 388 Increment/Decrement Instructions Section 3-10 specified words is incremented only when the execution condition has gone from OFF to ON. Wd+1 Wd+1 The Equals Flag will be turned ON if the result is 0000 0000 and the Carry Flag will be turned ON when a digit changes from 9 to 0. Both the Equals Flag and the Carry Flag will be turned ON when the content of changes from 9999 9999 to 0000 0000.
Page 389 Increment/Decrement Instructions Section 3-10 3-10-7 DECREMENT BCD: – –B(596) Purpose Decrements the 4-digit BCD content of the specified word by 1. Ladder Symbol − −B(596) Wd: Word Variations Variations Executed Each Cycle for ON Condition – –B(596) Executed Once for Upward Differentiation @–...
Page 390 Increment/Decrement Instructions Section 3-10 −1 The Equals Flag will be turned ON if the result is 0000 and the Carry Flag will be turned ON when a digit changes from 0 to 9. Flags Name Label Operation Error Flag ON if the content of Wd is not BCD. OFF in all other cases.
Page 391 Increment/Decrement Instructions Section 3-10 3-10-8 DOUBLE DECREMENT BCD: – –BL(597) Purpose Decrements the 8-digit BCD content of the specified words by 1. Ladder Symbol − −BL(597) Wd: First word Variations Variations Executed Each Cycle for ON Condition – –BL(597) Executed Once for Upward Differentiation @–...
Page 392 Increment/Decrement Instructions Section 3-10 of the specified words is decremented only when the execution condition has gone from OFF to ON. Wd+1 Wd+1 The Equals Flag will be turned ON if the result is 0000 0000 and the Carry Flag will be turned ON when a digit changes from 0 to 9. Flags Name Label...
Page 393: Symbol Math Instructions
Symbol Math Instructions Section 3-11 3-11 Symbol Math Instructions This section describes the Symbol Math Instructions, which perform arith- metic operations on BCD or binary data. Instruction Mnemonic Function code Page SIGNED BINARY ADD WITH- OUT CARRY DOUBLE SIGNED BINARY ADD WITHOUT CARRY SIGNED BINARY ADD WITH CARRY...
Page 394 Symbol Math Instructions Section 3-11 3-11-1 SIGNED BINARY ADD WITHOUT CARRY: +(400) Purpose Adds 4-digit (single-word) hexadecimal data and/or constants. Ladder Symbol +(400) Au: Augend word Ad: Addend word R: Result word Variations Variations Executed Each Cycle for ON Condition +(400) Executed Once for Upward Differentiation @+(400)
Page 395 Symbol Math Instructions Section 3-11 Description +(400) adds the binary values in Au and Ad and outputs the result to R. (Signed binary) (Signed binary) CY will turn ON when there (Signed binary) is a carry. Flags Name Label Operation Error Flag Equals Flag ON when the result is 0.
Page 396 Symbol Math Instructions Section 3-11 3-11-2 DOUBLE SIGNED BINARY ADD WITHOUT CARRY: +L(401) Purpose Adds 8-digit (double-word) hexadecimal data and/or constants. Ladder Symbol +L(401) Au: 1st augend word Ad: 1st addend word R: 1st result word Variations Variations Executed Each Cycle for ON Condition +L(401) Executed Once for Upward Differentiation @+L(401)
Page 397 Symbol Math Instructions Section 3-11 Description +L(401) adds the binary values in Au and Au+1 and Ad and Ad+1 and outputs the result to R. (Signed binary) Au+1 (Signed binary) Ad+1 CY will turn (Signed binary) ON when there is a carry. Flags Name Label...
Page 398 Symbol Math Instructions Section 3-11 3-11-3 SIGNED BINARY ADD WITH CARRY: +C(402) Purpose Adds 4-digit (single-word) hexadecimal data and/or constants with the Carry Flag (CY). Ladder Symbol +C(402) Au: Augend word Ad: Addend word R: Result word Variations Variations Executed Each Cycle for ON Condition +C(402) Executed Once for Upward Differentiation @+C(402)
Page 399 Symbol Math Instructions Section 3-11 Description +C(402) adds the binary values in Au, Ad, and CY and outputs the result to R. (Signed binary) (Signed binary) CY will turn ON when there (Signed binary) is a carry. Flags Name Label Operation Error Flag Equals Flag...
Page 400 Symbol Math Instructions Section 3-11 3-11-4 DOUBLE SIGNED BINARY ADD WITH CARRY: +CL(403) Purpose Adds 8-digit (double-word) hexadecimal data and/or constants with the Carry Flag (CY). Ladder Symbol +CL(403) Au: 1st augend word Ad: 1st addend word R: 1st result word Variations Variations Executed Each Cycle for ON Condition...
Page 401 Symbol Math Instructions Section 3-11 Description +CL(403) adds the binary values in Au and Au+1, Ad and Ad+1, and CY and outputs the result to R. (Signed binary) Au+1 (Signed binary) Ad+1 CY will turn ON when there (Signed binary) is a carry.
Page 402 Symbol Math Instructions Section 3-11 3-11-5 BCD ADD WITHOUT CARRY: +B(404) Purpose Adds 4-digit (single-word) BCD data and/or constants. Ladder Symbol +B(404) Au: Augend word Ad: Addend word R: Result word Variations Variations Executed Each Cycle for ON Condition +B(404) Executed Once for Upward Differentiation @+B(404) Executed Once for Downward Differentiation Not supported.
Page 403 Symbol Math Instructions Section 3-11 Description +B(404) adds the BCD values in Au and Ad and outputs the result to R. (BCD) (BCD) CY will turn (BCD) ON when there is a carry. Flags Name Label Operation Error Flag ON when Au is not BCD. ON when Ad is not BCD.
Page 404 Symbol Math Instructions Section 3-11 Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 A448 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area...
Page 405 Symbol Math Instructions Section 3-11 Precautions If Au, Au +1 or Ad, Ad +1 are not BCD, an error is generated and the Error Flag will turn ON. If as a result of the addition, the content of R, R +1 is 00000000 hex, the Equals Flag will turn ON.
Page 406 Symbol Math Instructions Section 3-11 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 407 Symbol Math Instructions Section 3-11 3-11-8 DOUBLE BCD ADD WITH CARRY: +BCL(407) Purpose Adds 8-digit (double-word) BCD data and/or constants with the Carry Flag (CY). Ladder Symbol +BCL(407) Au: 1st augend word Ad: 1st addend word R: 1st result word Variations Variations Executed Each Cycle for ON Condition...
Page 408 Symbol Math Instructions Section 3-11 Description +BCL(407) adds the BCD values in Au and Au+1, Ad and Ad+1, and CY and outputs the result to R, R+1. Au +1 (BCD) (BCD) Ad+1 CY will turn (BCD) ON when there is a carry. Flags Name Label...
Page 409 Symbol Math Instructions Section 3-11 Applicable Program Areas Block program Step program Subroutines Interrupt tasks areas areas Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959 A448 to A959 Timer Area...
Page 410 Symbol Math Instructions Section 3-11 Name Label Operation Carry Flag ON when the subtraction results in a borrow. OFF in all other cases. Overflow Flag ON when the result of subtracting a negative number from a positive number is in the range 8000 to FFFF hex. OFF in all other cases.
Page 411 Symbol Math Instructions Section 3-11 Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 A448 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area...
Page 412 Symbol Math Instructions Section 3-11 Name Label Operation Underflow Flag ON when the result of subtracting a positive number from a negative number is in the range 00000000 to 7FFFFFFF hex. OFF in all other cases. Negative Flag ON when the leftmost bit of the result is 1. OFF in all other cases.
Page 413 Symbol Math Instructions Section 3-11 Signed data Unsigned data Example 1 −1 FFFF Hex 65535 Note 1. Since the Negative Flag is ON, the result (FFFE hex) is a −) −) −) 0001 Hex negative value (2's complement) and is thus −2. −2 Note 1 FFFE Hex 65534 Note 2...
Page 414 Symbol Math Instructions Section 3-11 Subtraction at 2 Su+1: D00101 Su: D00100 − F 9 2 D R+1: D00101 R+1: D00100 Final Subtraction Result Mi+1: CIO 0201 Mi: CIO 0200 2 0 F 5 Su+1: D00101 Su: D00100 − F 9 2 D R+1: D00101 R+1: D00100 The Carry Flag (CY) is turned ON, so the actual number is –97AE06D3.
Page 415 Symbol Math Instructions Section 3-11 Area Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary...
Page 416 Symbol Math Instructions Section 3-11 Precautions When –C(412) is executed, the Error Flag will turn OFF. If as a result of the subtraction, the content of R is 0000 hex, the Equals Flag will turn ON. If the subtraction results in a borrow, the Carry Flag will turn ON. If the result of subtracting a negative number and CY from a positive number is negative (in the range 8000 to FFFF hex), the Overflow Flag will turn ON.
Page 417 Symbol Math Instructions Section 3-11 Area DM Area D00000 to D32766 EM Area without bank E00000 to E32766 EM Area with bank En_00000 to En_32766 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C)
Page 418 Symbol Math Instructions Section 3-11 Precautions When –CL(413) is executed, the Error Flag will turn OFF. If as a result of the subtraction, the content of R, R+1 is 00000000 hex, the Equals Flag will turn ON. If the subtraction results in a borrow, the Carry Flag will turn ON. If the result of subtracting a negative number and CY from a positive number is negative (in the range 80000000 to FFFFFFFF hex), the Overflow Flag will turn ON.
Page 419 Symbol Math Instructions Section 3-11 3-11-13 BCD SUBTRACT WITHOUT CARRY: –B(414) Purpose Subtracts 4-digit (single-word) BCD data and/or constants. Ladder Symbol –B(414) Mi: Minuend word Su: Subtrahend word R: Result word Variations Variations Executed Each Cycle for ON Condition –B(414) Executed Once for Upward Differentiation @–B(414) Executed Once for Downward Differentiation Not supported.
Page 420 Symbol Math Instructions Section 3-11 Description –B(414) subtracts the BCD values in Su from Mi and outputs the result to R. If the result of the subtraction is negative, the result is output as a 10’s comple- ment. (BCD) (BCD) –...
Page 421 Symbol Math Instructions Section 3-11 Applicable Program Areas Block program Step program Subroutines Interrupt tasks areas areas Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 A448 to A958 Timer Area...
Page 422 Symbol Math Instructions Section 3-11 Name Label Operation Equals Flag ON when the result is 0. OFF in all other cases. Carry Flag ON when the subtraction results in a borrow. OFF in all other cases. Precautions If Mi, Mi +1 and/or Su, Su +1 are not BCD, an error is generated and the Error Flag will turn ON.
Page 423 Symbol Math Instructions Section 3-11 000000 RSET 002100 −BL 0200 0120 D00100 −BL #00000000 D00100 D00100 "−" display 002100 Subtraction at 1 Mi+1: CIO 0201 Mi: CIO 0200 0 9 5 8 Su+1: CIO 0121 Su: CIO 0120 – 09583960 + (100000000 – 17072641) R+1: D00101 R+1: D00100 9 2 5 1...
Page 424 Symbol Math Instructions Section 3-11 3-11-15 BCD SUBTRACT WITH CARRY: –BC(416) Purpose Subtracts 4-digit (single-word) BCD data and/or constants with the Carry Flag (CY). Ladder Symbol –BC(416) Mi: Minuend word Su: Subtrahend word R: Result word Variations Variations Executed Each Cycle for ON Condition –BC(416) Executed Once for Upward Differentiation @–BC(416)
Page 425 Symbol Math Instructions Section 3-11 Description –BC(416) subtracts BCD values in Su and CY from Mi and outputs the result to R. If the result is negative, it is output to R as a 2’s complement. (BCD) (BCD) – CY will turn (BCD) ON when there is a borrow.
Page 426 Symbol Math Instructions Section 3-11 Variations Variations Executed Each Cycle for ON Condition –BCL(417) Executed Once for Upward Differentiation @–BCL(417) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program Step program Subroutines Interrupt tasks areas areas...
Page 427 Symbol Math Instructions Section 3-11 Flags Name Label Operation Error Flag ON when Mi and/or Mi +1 are not BCD. ON when Su and/or Su +1 are not BCD. OFF in all other cases. Equals Flag ON when the result is 0. OFF in all other cases.
Page 428 Symbol Math Instructions Section 3-11 Variations Variations Executed Each Cycle for ON Condition *(420) Executed Once for Upward Differentiation @*(420) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program Step program Subroutines Interrupt tasks areas areas...
Page 429 Symbol Math Instructions Section 3-11 Flags Name Label Operation Error Flag Equals Flag ON when the result is 0. OFF in all other cases. Negative Flag ON when the leftmost bit of the result is 1. OFF in all other cases. Precautions When *(420) is executed, the Error Flag will turn OFF.
Page 430 Symbol Math Instructions Section 3-11 Area Counter Area C0000 to C4094 C0000 to C4092 DM Area D00000 to D32766 D00000 to D32764 EM Area without bank E00000 to E32766 E00000 to E32764 EM Area with bank En_00000 to En_32766 En_00000 to En_32764 (n = 0 to C) (n = 0 to C)
Page 431 Symbol Math Instructions Section 3-11 Examples When CIO 000000 is ON in the following example, D00100, D00110, D00111, and D00110 will be multiplied as 8-digit signed hexadecimal values and the result will be output to D00121 and D00120. 3-11-19 UNSIGNED BINARY MULTIPLY: *U(422) Purpose Multiplies 4-digit unsigned hexadecimal data and/or constants.
Page 432 Section 3-11 Symbol Math Instructions Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_ 32767 (n = 0 to C) Constants #0000 to #FFFF (binary) Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15...
Page 433 Section 3-11 Symbol Math Instructions 3-11-20 DOUBLE UNSIGNED BINARY MULTIPLY: *UL(423) Purpose Multiplies 8-digit unsigned hexadecimal data and/or constants. Ladder Symbol *UL(423) Md: 1st multiplicand word Mr: 1st multiplier word R: 1st result word Variations Variations Executed Each Cycle for ON Condition *UL(423) Executed Once for Upward Differentiation @*UL(423)
Page 434 Symbol Math Instructions Section 3-11 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description *UL(423) multiplies the unsigned binary values in Md and Md+1 and Mr and Mr+1 and outputs the result to R, R+1, R+2, and R+3.
Page 435 Section 3-11 Symbol Math Instructions Variations Variations Executed Each Cycle for ON Condition *B(424) Executed Once for Upward Differentiation @*B(424) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program Step program Subroutines Interrupt tasks areas areas...
Page 436 Symbol Math Instructions Section 3-11 Flags Name Label Operation Error Flag ON when Md is not BCD. ON when Mr is not BCD. OFF in all other cases. Equals Flag ON when the result is 0. OFF in all other cases. Precautions If Md and/or Mr are not BCD, an error will be generated and the Error Flag will turn ON.
Page 437 Symbol Math Instructions Section 3-11 Area DM Area D00000 to D32766 D00000 to D32764 EM Area without bank E00000 to E32766 E00000 to E32764 EM Area with bank En_00000 to En_32766 En_00000 to En_32764 (n = 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary...
Page 438 Section 3-11 Symbol Math Instructions Examples When CIO 000000 is ON in the following example, D00101, D00100, D00111, and D00110 will be multiplied as 8-digit unsigned BCD values and the result will be output to D00123, D00122, D00121 and D00120. 3-11-23 SIGNED BINARY DIVIDE: /(430) Purpose Divides 4-digit (single-word) signed hexadecimal data and/or constants.
Page 439 Symbol Math Instructions Section 3-11 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants #0000 to #FFFF #0001 to #FFFF (binary) (binary) Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers...
Page 440 Symbol Math Instructions Section 3-11 3-11-24 DOUBLE SIGNED BINARY DIVIDE: /L(431) Purpose Divides 8-digit (double-word) signed hexadecimal data and/or constants. Ladder Symbol /L(431) Dd: 1st dividend word Dr: 1st divisor word R: 1st result word Variations Variations Executed Each Cycle for ON Condition /L(431) Executed Once for Upward Differentiation @/L(431)
Page 441 Symbol Math Instructions Section 3-11 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description /L(431) divides the signed binary values in Dd and Dd+1 by those in Dr and Dr+1 and outputs the result to R, R+1, R+2, and R+3.
Page 442 Section 3-11 Symbol Math Instructions 3-11-25 UNSIGNED BINARY DIVIDE: /U(432) Purpose Divides 4-digit (single-word) unsigned hexadecimal data and/or constants. Ladder Symbol /U(432) Dd: Dividend word Dr: Divisor word R: Result word Variations Variations Executed Each Cycle for ON Condition /U(432) Executed Once for Upward Differentiation @/U(432) Executed Once for Downward Differentiation Not supported.
Page 443 Section 3-11 Symbol Math Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description /U(432) divides the unsigned binary values in Dd by those in Dr and outputs the quotient to R and the remainder to R+1.
Page 444 Symbol Math Instructions Section 3-11 3-11-26 DOUBLE UNSIGNED BINARY DIVIDE: /UL(433) Purpose Divides 8-digit (double-word) unsigned hexadecimal data and/or constants. Ladder Symbol /UL(433) Dd: 1st dividend word Dr: 1st divisor word R: 1st result word Variations Variations Executed Each Cycle for ON Condition /UL(433) Executed Once for Upward Differentiation @/UL(433)
Page 445 Section 3-11 Symbol Math Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description /UL(433) divides the unsigned binary values in Dd and Dd+1 by those in Dr and Dr+1 and outputs the quotient to R, R+1 and the remainder to R+2, and R+3.
Page 446 Symbol Math Instructions Section 3-11 3-11-27 BCD DIVIDE: /B(434) Purpose Divides 4-digit (single-word) BCD data and/or constants. Ladder Symbol /B(434) Dd: Dividend word Dr: Divisor word R: Result word Variations Variations Executed Each Cycle for ON Condition /B(434) Executed Once for Upward Differentiation @/B(434) Executed Once for Downward Differentiation Not supported.
Page 447 Symbol Math Instructions Section 3-11 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description /B(434) divides the BCD content of Dd by those of Dr and outputs the quotient to R and the remainder to R+1.
Page 448 Section 3-11 Symbol Math Instructions 3-11-28 DOUBLE BCD DIVIDE: /BL(435) Purpose Divides 8-digit (double-word) BCD data and/or constants. Ladder Symbol /BL(435) Dd: 1st dividend word Dr: 1st divisor word R: 1st result word Variations Variations Executed Each Cycle for ON Condition /BL(435) Executed Once for Upward Differentiation @/BL(435)
Page 449: Conversion Instructions
Conversion Instructions Section 3-12 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description /BL(435) divides BCD values in Dd and Dd+1 by those in Dr and Dr+1 and outputs the quotient to R, R+1 and the remainder to R+2, R+3.
Page 450 Conversion Instructions Section 3-12 Instruction Mnemonic Function code Page 16-BIT TO 32-BIT SIGNED SIGN BINARY DATA DECODER MLPX DATA ENCODER DMPX ASCII CONVERT ASCII TO HEX COLUMN TO LINE LINE LINE TO COLUMN COLM SIGNED BCD-TO-BINARY BINS DOUBLE SIGNED BCD-TO- BISL BINARY SIGNED BINARY-TO-BCD...
Page 451 Conversion Instructions Section 3-12 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++)
Page 452 Conversion Instructions Section 3-12 Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 A448 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area D00000 to D32766...
Page 453 Conversion Instructions Section 3-12 S+1: CIO 0011 S: CIO 0010 200050=3X16 +13X16 +7X16 +2X16 R+1: D00201 R: D00200 3-12-3 BINARY-TO-BCD: BCD(024) Purpose Converts a word of binary data to a word of BCD data. Ladder Symbol BCD(024) S: Source word R: Result word Variations Variations...
Page 454 Conversion Instructions Section 3-12 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 455 Conversion Instructions Section 3-12 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands S: First Source Word The content of S+1 and S must be between 0000 0000 and 05F5 E0FF hexa- decimal (0000 0000 and 9999 9999 decimal). Operand Specifications Area CIO Area...
Page 456 Conversion Instructions Section 3-12 Examples The following diagram shows an example of 8-digit BCD-to-binary conversion. ×16 ×16 ×16 ×16 ×16 ×16 ×16 ×16 ×10 ×10 ×10 ×10 ×10 ×10 ×10 ×10 When CIO 000000 is ON in the following example, the hexadecimal value in CIO 0011 and CIO 0010 is converted to a BCD value and stored in D00200 and D00201.
Page 457 Conversion Instructions Section 3-12 Area EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD...
Page 458 Conversion Instructions Section 3-12 Example When CIO 000000 is ON in the following example, NEG(160) calculates the 2’s complement of the content of D00100 and writes the result to D00200. Actual Equivalent calculation subtraction Reverse bit status −) Add 1 3-12-6 DOUBLE 2’S COMPLEMENT: NEGL(161) Purpose Calculates the 2’s complement of two words of hexadecimal data.
Page 459 Conversion Instructions Section 3-12 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants #00000000 to #FFFFFFFF (binary) Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++)
Page 460 Conversion Instructions Section 3-12 3-12-7 16-BIT TO 32-BIT SIGNED BINARY: SIGN(600) Purpose Expands a 16-bit signed binary value to its 32-bit equivalent. Ladder Symbol SIGN(600) S: Source word R: First result word Variations Variations Executed Each Cycle for ON Condition SIGN(600) Executed Once for Upward Differentiation @SIGN(600)
Page 461 Conversion Instructions Section 3-12 Description SIGN(600) converts the 16-bit signed binary number in S to its 32-bit signed binary equivalent and writes the result in R+1 and R. The conversion is accomplished by copying the content of S to R and writing FFFF to R+1 if bit 15 of S is 1 or writing 0000 to R+1 if bit 15 of S is 0.
Page 462 Section 3-12 Conversion Instructions Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands S: Source Word The data in the source word indicates the location of the bit(s) that will be turned ON. C: Control Word The control word specifies whether MLPX(076) will perform a 4-to-16 bit con- version or an 8-to-256 bit conversion, the number of digits or bytes to be con- verted, and the starting digit or byte.
Page 463 Section 3-12 Conversion Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description MLPX(076) can perform 4-to-16 bit or 8-to-256 bit conversions. Set the left- most digit of C to 0 to specify 4-to-16 bit conversion and set it to 1 to specify 8- to-256 bit conversion.
Page 464 Conversion Instructions Section 3-12 =1 (Convert 2 bytes.) n=1 (Start with second byte.) 8-to-256 bit decoding (Bit m of R to R+15 is turned ON.) R+14 R+15 R+16 R+17 R+30 R+31 When two bytes are being converted, MLPX(076) will read the bytes in S from right to left and will wrap around to the rightmost byte if the leftmost byte (byte 1) has been specified as the starting byte.
Page 465 Section 3-12 Conversion Instructions Bits 0 to 3: Starting digit (Digit 1) C: # Bits 4 to 7: Number of digits (3 digits) Digits S: 0100 Digit 1 contains 6, so bit 6 is turned ON. Digit 2 contains A, so bit 10 is turned ON. Digit 3 contains F, so bit 15 is turned ON.
Page 466 Conversion Instructions Section 3-12 3-12-9 DATA ENCODER: DMPX(077) Purpose FInds the location of the first or last ON bit within the source word (or 16-word range), and writes that value to the specified digit (or byte) in the result word. Ladder Symbol DMPX(077) S: First source word...
Page 467 Conversion Instructions Section 3-12 Area Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959 A448 to A959 A000 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767...
Page 468 Section 3-12 Conversion Instructions The following diagram shows some example values for C and the 16-to-4 bit conversions that they produce. C: #0011 C: #0030 C: #0013 Digit 3 Digit 2 Digit 1 Digit 0 Digit 3 Digit 2 Digit 1 Digit 0 Digit 3 Digit 2 Digit 1 Digit 0 C: #0032...
Page 469 Conversion Instructions Section 3-12 When two bytes are being converted, DMPX(077) will write the values to the bytes in R from right to left and will wrap around to the rightmost byte if the leftmost byte (byte 1) has been specified as the starting byte. The following diagram shows some example values for C and the 256-to-8 bit conversions that they produce.
Page 470 Conversion Instructions Section 3-12 C: # DMPX(077) finds the leftmost ON bits. Starting digit (Digit 1) Digits R: D00100 3-12-10 ASCII CONVERT: ASC(086) Purpose Converts 4-bit hexadecimal digits in the source word into their 8-bit ASCII equivalents. Ladder Symbol ASC(086) S: Source word Di: Digit designator D: First destination word...
Page 471 Conversion Instructions Section 3-12 Digit number: 3 2 1 0 Specifies the first digit in S to be converted (0 to 3). Number of digits to be converted (0 to 3) 0: 1 digit 1: 2 digits 2: 3 digits 3: 4 digits First byte of D to be used.
Page 472 Conversion Instructions Section 3-12 Description ASC(086) treats the contents of S as 4 hexadecimal digits, converts the des- ignated digit(s) of S into their 8-bit ASCII equivalents, and writes this data into the destination word(s) beginning with the specified byte in D. First digit to convert Number of digits (n+1)
Page 473 Conversion Instructions Section 3-12 Di: #0011 Di: #0112 Di: #0030 Digit 3 Digit 2 Digit 1 Digit 0 Digit 3 Digit 2 Digit 1 Digit 0 Digit 3 Digit 2 Digit 1 Digit 0 Leftmost Rightmost Leftmost Leftmost Rightmost Rightmost Leftmost Rightmost Di: #0130...
Page 474 Conversion Instructions Section 3-12 3-12-11 ASCII TO HEX: HEX(162) Purpose Converts up to 4 bytes of ASCII data in the source word to their hexadecimal equivalents and writes these digits in the specified destination word. Ladder Symbol HEX(162) S: First source word Di: Digit designator D: Destination word Variations...
Page 475 Conversion Instructions Section 3-12 Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area A000 to A959 A448 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767...
Page 476 Conversion Instructions Section 3-12 The following diagram shows the basic operation of HEX(162) with Di=0021. C: 0021 First byte to convert Left (1) Right (0) Number of digits (n+1) First digit to write Parity It is possible to specify the parity of the ASCII data for use in error control dur- ing data transmissions.
Page 477 Conversion Instructions Section 3-12 Flags Name Label Operation Error Flag ON if there is a parity error in the ASCII data. ON if the ASCII data in the source words is not equivalent to hexadecimal digits ON if the content of Di is not within the specified ranges. OFF in all other cases.
Page 478 Conversion Instructions Section 3-12 Starting digit in D: Digit 1 Number of bytes: 2 Starting byte in S: Rightmost Parity: Even Parity bits: Result in even parity S: D00100 Starting byte: rightmost Conversion Starting digit (digit 1) Not changed D: D00300 Number of bytes (2 bytes) Not changed 3-12-12 COLUMN TO LINE: LINE(063)
Page 479 Conversion Instructions Section 3-12 Operand Specifications Area CIO Area CIO 0000 to CIO 0000 to CIO 6143 CIO 6128 Work Area W000 to W496 W000 to W511 Holding Bit Area H000 to H496 H000 to H511 Auxiliary Bit Area A000 to A944 A000 to A959 A448 to A959 Timer Area...
Page 480 Conversion Instructions Section 3-12 Flags Name Label Operation Error Flag ON if N is not within the specified range of 0000 to 000F. OFF in all other cases. Equals Flag ON if D is 0000 after execution. OFF in all other cases. Example When CIO 000000 is ON in the following example, LINE(063) copies bit 5 from D00100 to D00115 to the 16 bits in D00200.
Page 481 Conversion Instructions Section 3-12 N: Bit Number Specifies the bit number (0000 to 000F or &0 to &15) to be overwritten by the source word. Operand Specifications Area CIO Area CIO 0000 to CIO 0000 to CIO 0000 to CIO 6143 CIO 6128 CIO 6143 Work Area...
Page 482 Conversion Instructions Section 3-12 Description COLM(064) copies the 16 bits from S to the 16 bits with bit number N in the 16-word range D to D+15. Bit m of S is copied to bit N of D+m, i.e., bit 00 of S is copied to bit N of D and bit 15 of S is copied to bit N of D+15.
Page 483 Conversion Instructions Section 3-12 3-12-14 SIGNED BCD-TO-BINARY: BINS(470) Purpose Converts one word of signed BCD data to one word of signed binary data. Ladder Symbol BINS(470) C: Control word S: Source word D: Destination word Variations Variations Executed Each Cycle for ON Condition BINS(470) Executed Once for Upward Differentiation @BINS(470)
Page 484 Conversion Instructions Section 3-12 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description BINS(470) converts signed BCD data to signed binary data. First the signed BCD data format and range in word S are checked against the setting in the control word (C).
Page 485 Conversion Instructions Section 3-12 C = 0003 (Input Data Range: –1999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (−1) F: Negative (−) B to E: Error The following table shows the possible BCD values for each signed BCD for- mat and the corresponding signed binary values.
Page 486 Conversion Instructions Section 3-12 3-12-15 DOUBLE SIGNED BCD-TO-BINARY: BISL(472) Purpose Converts double signed BCD data to double signed binary data. Ladder Symbol BISL(472) C: Control word S: First source word D: First destination word Variations Variations Executed Each Cycle for ON Condition BISL(472) Executed Once for Upward Differentiation @BISL(472)
Page 487 Conversion Instructions Section 3-12 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description BISL(472) converts the double signed BCD data in S+1 and S to double signed binary data and writes the result in D+1 and D.
Page 488 Conversion Instructions Section 3-12 C = 0002 (Input Data Range: –999 9999 to 9999 9999 BCD) 7 digits BCD, 28 bits 0 to 9: Eighth digit BCD F: Negative (–) A to E: Error C = 0003 (Input Data Range: –1999 9999 to 9999 9999 BCD) 7 digits BCD, 28 bits 0 to 9: Eighth digit BCD A: Negative (–1)
Page 489 Conversion Instructions Section 3-12 3-12-16 SIGNED BINARY-TO-BCD: BCDS(471) Purpose Converts one word of signed binary data to one word of signed BCD data. Ladder Symbol BCDS(471) C: Control word S: Source word D: Destination word Variations Variations Executed Each Cycle for ON Condition BCDS(471) Executed Once for Upward Differentiation @BCDS(471)
Page 490 Conversion Instructions Section 3-12 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 491 Conversion Instructions Section 3-12 C = 0002 (Output Data Range: –999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD F: Negative (–) C = 0003 (Output Data Range: –1999 to 9999 BCD) 3 digits BCD, 12 bits 0 to 9: Fourth digit BCD A: Negative (–1) F: Negative (–)
Page 492 Section 3-12 Conversion Instructions Variations Variations Executed Each Cycle for ON Condition BDSL(473) Executed Once for Upward Differentiation @BDSL(473) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Operands C: Control Word Specifies the signed BCD format. C must be 0000 to 0003. S: First Source Word Source words S+1 and S contain the double signed binary data to be con- verted.
Page 493 Section 3-12 Conversion Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description BDSL(473) converts double signed binary data to double signed BCD data. First the double signed binary data in S+1 and S is checked to verify that it is within the valid range for the signed BCD format specified in the control word (C).
Page 494 Conversion Instructions Section 3-12 C = 0003 (Output Data Range: –1999 9999 to 9999 9999 BCD) 7 digits BCD, 28 bits 0 to 9: Eighth digit BCD A: Negative (–1) F: Negative (–) The following table shows the possible double signed binary values for each signed BCD format.
Page 495: Logic Instructions
Section 3-13 Logic Instructions 3-13 Logic Instructions This section describes instructions which perform logic operations on word data. Instruction Mnemonic Function code Page LOGICAL AND ANDW DOUBLE LOGICAL AND ANDL LOGICAL OR DOUBLE LOGICAL OR ORWL EXCLUSIVE OR XORW DOUBLE EXCLUSIVE OR XORL EXCLUSIVE NOR XNRW...
Page 496 Section 3-13 Logic Instructions Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 497 Section 3-13 Logic Instructions 3-13-2 DOUBLE LOGICAL AND: ANDL(610) Purpose Takes the logical AND of corresponding bits in double words of word data and/ or constants. Ladder Symbol ANDL(610) : Input 1 : Input 2 R: Result word Variations Variations Executed Each Cycle for ON Condition ANDL(610) Executed Once for Upward Differentiation...
Page 498 Section 3-13 Logic Instructions Description ANDL(610) takes the logical AND of data specified in I +1 and I +1 and outputs the result to R, R+1. +1) → (R, R+1) +1), (I R, R+1 Flags Name Label Operation Error Flag Equals Flag ON when the result is 0.
Page 499 Section 3-13 Logic Instructions Variations Variations Executed Each Cycle for ON Condition ORW(035) Executed Once for Upward Differentiation @ORW(035) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications...
Page 500 Section 3-13 Logic Instructions Flags Name Label Operation Error Flag Equals Flag ON when the result is 0. OFF in all other cases. Negative Flag ON when the leftmost bit of R is 1. OFF in all other cases. Precautions When ORW(035) is executed, the Error Flag will turn OFF.
Page 501 Section 3-13 Logic Instructions Area EM Area with bank En_00000 to En_32766 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD...
Page 502 Section 3-13 Logic Instructions Examples When the execution condition CIO 00000000 is ON, the logical OR is taken of corresponding bits in CIO 0021, CIO 0020 and CIO 0301, CIO 0300 and the results will be output to corresponding bits in D00501 and D00500. 0020 CH 0300 CH D00500...
Page 503 Section 3-13 Logic Instructions Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 504 Section 3-13 Logic Instructions 3-13-6 DOUBLE EXCLUSIVE OR: XORL(612) Purpose Takes the logical exclusive OR of corresponding bits in double words of word data and/or constants. Ladder Symbol XORL(612) : Input 1 : Input 2 R: Result word Variations Variations Executed Each Cycle for ON Condition XORL(612) Executed Once for Upward Differentiation...
Page 505 Section 3-13 Logic Instructions Description XORL(612) takes the logical exclusive OR of data specified in I and I double-word data and outputs the result to R, R+1. • When the content of any of the corresponding bits in I +1, I and I +1are different, a 1 will be output to the corresponding bit it R, R+1.
Page 506 Section 3-13 Logic Instructions 3-13-7 EXCLUSIVE NOR: XNRW(037) Purpose Takes the logical exclusive NOR of corresponding single words of word data and/or constants. Ladder Symbol XNRW(037) : Input 1 : Input 2 R: Result word Variations Variations Executed Each Cycle for ON Condition XNRW(037) Executed Once for Upward Differentiation @XNRW(037)
Page 507 Section 3-13 Logic Instructions Description XNRW(037) takes the logical exclusive NOR of data specified in I and I outputs the result to R. • The logical exclusive NOR is taken of corresponding bits in I and I succession. • When the content of corresponding bits of I and I are different, a 0 will be output to the corresponding bit of R and when they are different, 1 will...
Page 508 Section 3-13 Logic Instructions Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 toW 510 Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 A448 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area D00000 to D32766...
Page 509 Section 3-13 Logic Instructions Precautions When XNRL(613) is executed, the Error Flag will turn OFF. If as a result of the exclusive NOR, the content of R, R+1 is 00000000 Hex, the Equals Flag will turn ON. If as a result of the exclusive NOR, the leftmost bit of R+1 is 1, the Negative Flag will turn ON.
Page 510 Section 3-13 Logic Instructions Area EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767...
Page 511 Section 3-13 Logic Instructions 3-13-10 DOUBLE COMPLEMENT: COML(614) Purpose Turns OFF all ON bits and turns ON all OFF bits in Wd and Wd+1. Ladder Symbol COML(614) Wd: Word Variations Variations Executed Each Cycle for ON Condition COML(614) Executed Once for Upward Differentiation @COML(614) Executed Once for Downward Differentiation Not supported.
Page 512: Special Math Instructions
Section 3-14 Special Math Instructions Flags Name Label Operation Error Flag Equals Flag ON when the result is 0. OFF in all other cases. Negative Flag ON when the leftmost bit of R is 1. OFF in all other cases. Precautions When COML(614) is executed, the Error Flag will turn OFF.
Page 513 Section 3-14 Special Math Instructions Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications Area CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143 Work Area W000 to W510 W000 to W511 Holding Bit Area H000 to H510 H000 to H511...
Page 514 Section 3-14 Special Math Instructions Flags Name Label Operation Error Flag ON if bit 15 of S+1 is 1 (ON). OFF in all other cases. Equals Flag ON if the result is 0000. OFF in all other cases. Overflow Flag ON if the content of S+1 and S is 4000 0000 to 7FFF FFFF.
Page 515 Section 3-14 Special Math Instructions Area Timer Area T0000 to T4094 T0000 to T4095 Counter Area C0000 to C4094 C0000 to C4095 DM Area D00000 to D32766 D00000 to D32767 EM Area without bank E00000 to E32766 E00000 to E32767 EM Area with bank En_00000 to En_32766 En_00000 to En_32767...
Page 516 Section 3-14 Special Math Instructions Truncated Square Root of a 4-digit Number The following example shows how to take the square root of a 4-digit number and round off the result. This program example calculates the square root of the 4-digit number in CIO 0010, rounds off the result, and writes it to CIO 0011.
Page 517 Section 3-14 Special Math Instructions The values after the decimal point should be rounded. @BSET @MOV @ROOT @MOV @MOV @MOVD @MOVD @INC 1,2,3... 1. The source words (D00101 and D00100) to be are cleared to 0000 0000. D00101 D00100 0000 0000 2.
Page 518 Section 3-14 Special Math Instructions D00101 D00100 6017 0000 7 756.932 … 60 170 000 D00100 Square root computation (Remainder eliminated) 7756 4. D00103 and the result word, CIO 0011, are cleared to 0000 0000. D00103 CIO 0011 0000 0000 5.
Page 519 Section 3-14 Special Math Instructions Operands Sine Function (C = 0000 Hex) Operand Value Data range 0000 Hex 0000 to 0900 (BCD) 0° to 90° 0000 to 9999 (BCD) 0.0000 to 0.9999 9999 (BCD) 1.0000 Cosine Function (C = 0001 Hex) Operand Value Data range...
Page 520 Section 3-14 Special Math Instructions Area EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD...
Page 521 Section 3-14 Special Math Instructions binary. In CS1-H, CJ1-H, and CJ1M CPU Units, the source data can also be signed binary data or floating-point data. Unsigned Integer Data (Binary or BCD) 14 13 12 11 Number of coordinates minus one (m-1), 00 to FF Hex (1 ≤...
Page 522 Section 3-14 Special Math Instructions 15 determines whether the input is BCD or binary: OFF specifies binary and ON specifies BCD. 16-bit BCD16-bit binary (signed Floating-point data 32-bit signed binary data or unsigned) or 16-bit BCD data X0 (rightmost 16 bits) X0 (rightmost 16 bits) X0 (*1) X0 (leftmost 16 bits)
Page 523 Section 3-14 Special Math Instructions Y (binary data) Equation: −Y f(Y)= (S−X −X Calculation −Y result −X S−X X (binary data) Input data 3. X < S Converted value = Y Up to 256 endpoints can be stored in the line-segment data table beginning at C+1.
Page 524 Section 3-14 Special Math Instructions • 16-bit Unsigned Binary Data The input data and/or the output data can be 16-bit unsigned binary data. Also, the linear extrapolation function can be set to operate on the value specified in S directly or on X –S.
Page 525 Section 3-14 Special Math Instructions Flags Name Label Operation Error Flag ON if C is a constant greater than 0001. ON if C is a word address but the X coordinates are not in ≤ X ≤ ... ≤ X ascending order (X ON if C is a word address and bits 9, 11, and 15 of C indi- cate BCD input, but S is not BCD.
Page 526 Section 3-14 Special Math Instructions Linear Extrapolation (C: Word Address) Using 16-bit Unsigned BCD or Binary Data APR(069) processes the input data specified in S based on the control data in C and the line-segment data specified in the table beginning at C+1. The result is output to D.
Page 527 Section 3-14 Special Math Instructions $1F20 $0F00 (x,y) $0726 $0402 (0,0) $0005 $0014 $001A $05F0 The linear-extrapolation calculation is shown below. 0402 0F00 – × -------------------------------- - 0F00 0014 0015 – 001A 0005 – × 000F ) 0F00 0086 – 0726 Values are all hexadecimal (Hex).
Page 528 Section 3-14 Special Math Instructions Linear Extrapolation (C: Word Address) Using 32-bit Signed Binary Data (CS1-H/CJ1-H/CJ1M Only) In this example, APR(069) is used to convert the fluid height in a tank to fluid volume based on the shape of the holding tank. Fluid height to volume conversion table (32-bit signed binary data)
Page 529 Section 3-14 Special Math Instructions Linear Extrapolation (C: Word Address) Using Floating-point Data (CS1-H/CJ1-H/CJ1M Only) In this example, APR(069) is used to convert the fluid height in a tank to fluid volume based on the shape of the holding tank. X0 (rightmost 16 bits) Fluid height to volume X0 (leftmost 16 bits)
Page 530 Section 3-14 Special Math Instructions 3-14-4 FLOATING POINT DIVIDE: FDIV(079) Purpose Divides one 7-digit floating-point number by another. The floating-point num- bers are expressed in scientific notation (7-digit mantissa and 1-digit expo- nent). Ladder Symbol FDIV(079) Dd: First dividend word Dr: First divisor word R: First result word Variations...
Page 531 Section 3-14 Special Math Instructions Description FDIV(079) divides the floating-point value in Dd and Dd+1 by that in Dr and Dr+1 and places the result in R and R+1. Quotient Dr+1 Dd+1 To represent the floating-point values, the rightmost seven digits are used for the mantissa and the leftmost digit is used for the exponent, as shown in the diagram below.
Page 532 Section 3-14 Special Math Instructions Examples Basic Floating-point Division When CIO 000000 is ON in the following example, FDIV(079) divides the floating-point number in D00101 and D00100 by the floating-point number in CIO 0021 and CIO 0020 and writes the result to D00301 and D00300. D00101 D00100 0.5670000 ×...
Page 533 Section 3-14 Special Math Instructions @MOV @MOV @MOV @MOV @MOVD @MOVD @MOVD @MOVD @FDIV 1,2,3... 1. D00100 and D00102 are set to 0000. 2. D00101 and D00103 are set to 4000. D00101 D00100 D00103 D00102 4000 0000 4000 0000 3. MOVD(083) is used to move the digits of the original source words to the proper digits in the 2-word floating-point formats.
Page 534 Section 3-14 Special Math Instructions D00000 D00001 D00101 D00100 D00103 D00102 4. FDIV(079) divides the floating-point number in D00101 and D00100 by the floating-point number in D00103 and D00102. D00101 D00100 0.3452000 × 10 ÷ D00103 D00102 0.0079000 × 10 D00003 D00002 0.4369620 ×...
Page 535 Section 3-14 Special Math Instructions Area EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM...
Page 536: Floating-Point Math Instructions
Section 3-15 Floating-point Math Instructions 3-15 Floating-point Math Instructions The Floating-point Math Instructions convert data and perform floating-point arithmetic operations. CS/CJ-series CPU Units support the following instruc- tions. Instruction Mnemonic Function code Page FLOATING TO 16-BIT FLOATING TO 32-BIT FIXL 16-BIT TO FLOATING 32-BIT TO FLOATING FLTL...
Page 537 Section 3-15 Floating-point Math Instructions The floating-point data format conforms to the IEEE754 standards. Data is expressed in 32 bits, as follows: Sign Exponent Mantissa Data No. of bits Contents s: sign 0: positive; 1: negative e: exponent The exponent (e) value ranges from 0 to 255. The actual exponent is the value remaining after 127 is subtracted from e, resulting in a range of –...
Page 538 Section 3-15 Floating-point Math Instructions Numbers Expressed as Floating-point Values The following types of floating-point numbers can be used. Mantissa (f) Exponent (e) Not 0 and All 1’s (255) not all 1’s Normalized number Infinity Not 0 Non-normalized number Note A non-normalized number is one whose absolute value is too small to be expressed as a normalized number.
Page 539 Section 3-15 Floating-point Math Instructions NaN (not a number) is produced when the result of calculations, such as 0.0/ 0.0, ∞ / ∞ , or ∞ – ∞ , does not correspond to a number or infinity. The exponent will be 255 (2 –...
Page 540 Section 3-15 Floating-point Math Instructions P (100, 100) θ 000000 D00000 D00200 D00001 D00201 D00200 D00202 D00201 D00204 D00202 D00202 D00206 D00204 D00204 D00208 D00206 D00208 D00210 D00210 D00212 D00204 D00202 D00214 D00214 D00216 D00216 D00218 D00212 D00220 D00218 D00221 D00220 D00100 D00221...
Page 541 Section 3-15 Floating-point Math Instructions Calculations Example Distance r = Distance r = = 141.4214 χ Angle = tan Angle = tan = 45.0 DM Contents D00000 #0100 0 1 4 1 D00100 (BCD) (BCD) D00001 #0100 0 0 4 5 D00101 (BCD) (BCD)
Page 542 Section 3-15 Floating-point Math Instructions Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications Area CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6143 Work Area W000 to W510 W000 to W511 Holding Bit Area H000 to H510 H000 to H511...
Page 543 Section 3-15 Floating-point Math Instructions Flags Name Label Operation Error Flag ON if the data in S+1 and S is not a number (NaN). ON if the integer portion of S+1 and S is not within the range of –32,768 to 32,767. OFF in all other cases.
Page 544 Section 3-15 Floating-point Math Instructions Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants #00000000 to #FFFFFFFF (binary) Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++)
Page 545 Section 3-15 Floating-point Math Instructions Variations Variations Executed Each Cycle for ON Condition FLT(452) Executed Once for Upward Differentiation @FLT(452) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications...
Page 546 Section 3-15 Floating-point Math Instructions Example conversions: A signed binary value of 3 is converted to 3.0. A signed binary value of –3 is converted to –3.0. Flags Name Label Operation Error Flag Equals Flag ON if both the exponent and mantissa of the result are 0. OFF in all other cases.
Page 547 Section 3-15 Floating-point Math Instructions Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants #00000000 to #FFFFFFFF (binary) Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++)
Page 548 Section 3-15 Floating-point Math Instructions 3-15-5 FLOATING-POINT ADD: +F(454) Purpose Adds two 32-bit floating-point numbers and places the result in the specified result words. Ladder Symbol +F(454) Au: First augend word AD: First addend word R: First result word Variations Variations Executed Each Cycle for ON Condition +F(454)
Page 549 Section 3-15 Floating-point Math Instructions Description +F(454) adds the 32-bit floating-point number in Ad+1 and Ad to the 32-bit floating-point number in Au+1 and Au and places the result in R+1 and R. (The floating point data must be in IEEE754 format.) Au+1 Augend (floating-point data, 32 bits) Ad+1...
Page 550 Section 3-15 Floating-point Math Instructions 3-15-6 FLOATING-POINT SUBTRACT: –F(455) Purpose Subtracts one 32-bit floating-point number from another and places the result in the specified result words. Ladder Symbol –F(455) Mi: First Minuend word Su: First Subtrahend word R: First result word Variations Variations Executed Each Cycle for ON Condition...
Page 551 Section 3-15 Floating-point Math Instructions Description –F(455) subtracts the 32-bit floating-point number in Su+1 and Su from the 32-bit floating-point number in Mi+1 and Mi and places the result in R+1 and R. (The floating point data must be in IEEE754 format.) Mi+1 Minuend (floating-point data, 32 bits) –...
Page 552 Section 3-15 Floating-point Math Instructions 3-15-7 FLOATING-POINT MULTIPLY: *F(456) Purpose Multiplies two 32-bit floating-point numbers and places the result in the speci- fied result words. Ladder Symbol *F(456) Md: First Multiplicand word Mr: First Multiplier word R: First result word Variations Variations Executed Each Cycle for ON Condition...
Page 553 Section 3-15 Floating-point Math Instructions *F(456) multiplies the 32-bit floating-point number in Md+1 and Md by the 32- Description bit floating-point number in Mr+1 and Mr and places the result in R+1 and R. (The floating point data must be in IEEE754 format.) Md+1 Multiplicand (floating-point data, 32 bits) ×...
Page 554 Section 3-15 Floating-point Math Instructions 3-15-8 FLOATING-POINT DIVIDE: /F(457) Purpose Divides one 32-bit floating-point number by another and places the result in the specified result words. Ladder Symbol /F(457) Dd: First Dividend word Dr: First Divisor word R: First result word Variations Variations Executed Each Cycle for ON Condition...
Page 555 Section 3-15 Floating-point Math Instructions Description /F(457) divides the 32-bit floating-point number in Dd+1 and Dd by the 32-bit floating-point number in Dr+1 and Dr and places the result in R+1 and R. (The floating point data must be in IEEE754 format.) Dd+1 Dividend (floating-point data, 32 bits) ÷...
Page 556 Section 3-15 Floating-point Math Instructions 3-15-9 DEGREES TO RADIANS: RAD(458) Purpose Converts a 32-bit floating-point number from degrees to radians and places the result in the specified result words. Ladder Symbol RAD(458) S: First source word R: First result word Variations Variations Executed Each Cycle for ON Condition...
Page 557 Section 3-15 Floating-point Math Instructions Description RAD(458) converts the 32-bit floating-point number in S+1 and S from degrees to radians and places the result in R and R+1. (The floating point source data must be in IEEE754 format.) Source (degrees, 32-bit floating-point data) Result (radians, 32-bit floating-point data) Degrees are converted to radians by means of the following formula: Degrees ×...
Page 558 Section 3-15 Floating-point Math Instructions Operand Specifications Area CIO Area CIO 0000 to CIO 6142 Work Area W000 to W510 Holding Bit Area H000 to H510 Auxiliary Bit Area A000 to A958 A448 to A958 Timer Area T0000 to T4094 Counter Area C0000 to C4094 DM Area...
Page 559 Section 3-15 Floating-point Math Instructions Flags Name Label Operation Error Flag ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). OFF in all other cases. Equals Flag ON if both the exponent and mantissa of the result are 0. OFF in all other cases.
Page 560 Section 3-15 Floating-point Math Instructions Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants...
Page 561 Section 3-15 Floating-point Math Instructions Name Label Operation Underflow Flag Negative Flag ON if the result is negative. OFF in all other cases. Precautions The source data in S+1 and S must be in IEEE754 floating-point data format. 3-15-12 COSINE: COS(461) Purpose Calculates the cosine of a 32-bit floating-point number (in radians) and places the result in the specified result words.
Page 562 Section 3-15 Floating-point Math Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description COS(461) calculates the cosine of the angle (in radians) expressed as a 32- bit floating-point value in S+1 and S and places the result in R+1 and R.
Page 563 Section 3-15 Floating-point Math Instructions 3-15-13 TANGENT: TAN(462) Purpose Calculates the tangent of a 32-bit floating-point number (in radians) and places the result in the specified result words. Ladder Symbol TAN(462) S: First source word R: First result word Variations Variations Executed Each Cycle for ON Condition TAN(462)
Page 564 Section 3-15 Floating-point Math Instructions Description TAN(462) calculates the tangent of the angle (in radians) expressed as a 32- bit floating-point value in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.) Source (32-bit floating-point data) Result (32-bit floating-point data) Specify the desired angle (–65,535 to 65,535) in radians in S+1 and S.
Page 565 Section 3-15 Floating-point Math Instructions 3-15-14 ARC SINE: ASIN(463) Purpose Calculates the arc sine of a 32-bit floating-point number and places the result in the specified result words. (The arc sine function is the inverse of the sine function; it returns the angle that produces a given sine value between –1 and Ladder Symbol ASIN(463) S: First source word...
Page 566 Section 3-15 Floating-point Math Instructions Description ASIN(463) computes the angle (in radians) for a sine value expressed as a 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.) –1 Source (32-bit floating-point data) Result (32-bit floating-point data)
Page 567 Section 3-15 Floating-point Math Instructions 3-15-15 ARC COSINE: ACOS(464) Purpose Calculates the arc cosine of a 32-bit floating-point number and places the result in the specified result words. (The arc cosine function is the inverse of the cosine function; it returns the angle that produces a given cosine value between –1 and 1.) Ladder Symbol ACOS(464)
Page 568 Section 3-15 Floating-point Math Instructions Description ACOS(464) computes the angle (in radians) for a cosine value expressed as a 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.) –1 Source (32-bit floating-point data) Result (32-bit floating-point data)
Page 569 Section 3-15 Floating-point Math Instructions 3-15-16 ARC TANGENT: ATAN(465) Purpose Calculates the arc tangent of a 32-bit floating-point number and places the result in the specified result words. (The arc tangent function is the inverse of the tangent function; it returns the angle that produces a given tangent value.) Ladder Symbol ATAN(465) S: First source word...
Page 570 Section 3-15 Floating-point Math Instructions Description ATAN(465) computes the angle (in radians) for a tangent value expressed as a 32-bit floating-point number in S+1 and S and places the result in R+1 and (The floating point source data must be in IEEE754 format.) –1 Source (32-bit floating-point data) Result (32-bit floating-point data)
Page 571 Section 3-15 Floating-point Math Instructions 3-15-17 SQUARE ROOT: SQRT(466) Purpose Calculates the square root of a 32-bit floating-point number and places the result in the specified result words. Ladder Symbol SQRT(466) S: First source word R: First result word Variations Variations Executed Each Cycle for ON Condition SQRT(466)
Page 572 Section 3-15 Floating-point Math Instructions Description SQRT(466) calculates the square root of the 32-bit floating-point number in S+1 and S and places the result in R+1 and R. (The floating point source data must be in IEEE754 format.) Source (32-bit floating-point data) Result (32-bit floating-point data) The source data must be positive;...
Page 573 Section 3-15 Floating-point Math Instructions 3-15-18 EXPONENT: EXP(467) Purpose Calculates the natural (base e) exponential of a 32-bit floating-point number and places the result in the specified result words. Ladder Symbol EXP(467) S: First source word R: First result word Variations Variations Executed Each Cycle for ON Condition...
Page 574 Section 3-15 Floating-point Math Instructions Description EXP(467) calculates the natural (base e) exponential of the 32-bit floating- point number in S+1 and S and places the result in R+1 and R. In other words, EXP(467) calculates e (x = source) and places the result in R+1 and R. Source (32-bit floating-point data) Result (32-bit floating-point data) If the absolute value of the result is greater than the maximum value that can...
Page 575 Section 3-15 Floating-point Math Instructions 3-15-19 LOGARITHM: LOG(468) Purpose Calculates the natural (base e) logarithm of a 32-bit floating-point number and places the result in the specified result words. Ladder Symbol LOG(468) S: First source word R: First result word Variations Variations Executed Each Cycle for ON Condition...
Page 576 Section 3-15 Floating-point Math Instructions Description LOG(468) calculates the natural (base e) logarithm of the 32-bit floating-point number in S+1 and S and places the result in R+1 and R. Source (32-bit floating-point data) Result (32-bit floating-point data) The source data must be positive; if it is negative, an error will occur and the instruction won’t be executed.
Page 577 Section 3-15 Floating-point Math Instructions 3-15-20 EXPONENTIAL POWER: PWR(840) Purpose Raises a 32-bit floating-point number to the power of another 32-bit floating- point number. Ladder Symbol PWR(840) B: First base word E: First exponent word R: First result word Variations Variations Executed Each Cycle for ON Condition PWR(840)
Page 578 Section 3-15 Floating-point Math Instructions Description PWR(840) raises the 32-bit floating-point number in B+1 and B to the power of the 32-bit floating-point number in E+1 and E. In other words, PWR(840) calculates X (X = B+1 and B; Y = E+1 and E). Exponent data Base data For example, when the base words (B+1 and B) contain 3.1 and the exponent...
Page 579 Section 3-15 Floating-point Math Instructions Ladder Symbol Symbol & options : Comparison data 1 : Comparison data 2 Variations Variations Creates ON Each Cycle Comparison is True Input compari- son instruction Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks...
Page 580 Section 3-15 Floating-point Math Instructions Inputting the Instructions The input comparison instructions are treated just like the LD, AND, and OR instructions to control the execution of subsequent instructions. Input type Operation The instruction can be connected directly to the left bus bar. The instruction cannot be connected directly to the left bus bar.
Page 581 Section 3-15 Floating-point Math Instructions Code Mnemonic Name Function LD<>F LOAD FLOATING NOT EQUAL True if C1 ≠ C2 AND<>F AND FLOATING NOT EQUAL OR<>F OR FLOATING NOT EQUAL LD<F LOAD FLOATING LESS THAN True if C1 < C2 AND<F AND FLOATING LESS THAN OR<F OR FLOATING LESS THAN...
Page 582 Section 3-15 Floating-point Math Instructions 005000 000000 <F D00100 D00200 FLOATING LESS THAN Comparison (<F) S1 :D00100 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S2 :D00200 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S1+1:D00101 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 S2+1:D00201...
Page 583 Section 3-15 Floating-point Math Instructions Area Counter Area C0000 to C4094 C0000 to C4093 C0000 to C4095 DM Area D00000 to D32766 D00000 to D32765 D00000 to D32767 EM Area without bank E00000 to E32766 E00000 to E32765 E00000 to E32767 EM Area with bank En_00000 to En_00000 to...
Page 584 Section 3-15 Floating-point Math Instructions nent part. Example: 1.2456E-2 (1.2456 × 10 • The content of C+1 (Total characters) specifies the number of ASCII char- acters after conversion including the sign symbol, numbers, decimal point and spaces. • The content of C+2 (Fractional digits) specifies the number of digits (char- acters) below the decimal point.
Page 585 Section 3-15 Floating-point Math Instructions Storage of ASCII Text After the floating-point number is converted to ASCII text, the ASCII characters are stored in the destina- tion words beginning with D, as shown in the following diagrams. Different storage methods are used for decimal notation and scientific notation.
Page 586 Section 3-15 Floating-point Math Instructions a) Decimal Notation (C = 0000 Hex) • When there is no fractional part (C+2 = 0000 Hex): 1 ≤ Number of Integer Digits ≤ 24 • When there is a fractional part (C+2 = 0001 to 0007 Hex): 1 ≤...
Page 587 Section 3-15 Floating-point Math Instructions 000000 FSTR D00000 D00010 D00100 Conversion 1 0 1 0 1 0 0 0 0 1 1 1 0 0 1 0 D00000 0.327457 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 1 D00001 Decimal notation Storage...
Page 588 Section 3-15 Floating-point Math Instructions Ladder Symbol FVAL(449) S: First source word D: First destination word Variations Variations Executed Each Cycle for ON Condition FVAL(449) Executed Once for Upward Differentiation @FVAL(449) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported.
Page 589 Section 3-15 Floating-point Math Instructions • Decimal notation Real numbers expressed with an integer and fractional part. Example: 124.56 • Scientific notation Real numbers expressed as an integer part, fractional part, and exponent part. Example: 1.2456E-2 (1.2456 × 10 The data format (decimal or scientific notation) is detected automatically. The ASCII text must be stored in S and subsequent words in the following order: leftmost byte of S, rightmost byte of S, leftmost byte of S+1, rightmost byte of S+1, etc.
Page 590 Section 3-15 Floating-point Math Instructions Decimal notation 25 characters max. Sign (20) Integer part Fractional part Digit (20) Sign SP SP Decimal The 7th and higher digits are ignored. point (The sign, decimal point, and exponent characters are not counted as digits.) Any spaces (20 Hex) or zeroes (30 Hex) before the first digit are ignored.
Page 591: Double-Precision Floating-Point Instructions (Cs1-H, Cj1-H, Cj1M, Or Cs1D Only)
Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) 000000 FVAL D00000 D00100 The 7th and higher digits are ignored. (The sign, decimal point, and leading zeroes/spaces are not counted.) Ignored − 0 1 . 2 3 4 5 2 1 Conversion D00000 2D (−)
Page 592 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Instruction Mnemonic Function code Page DOUBLE FLOATING-POINT DIVIDE DOUBLE DEGREES TO RADIANS RADD DOUBLE RADIANS TO DEGREES DEGD DOUBLE SINE SIND DOUBLE COSINE COSD DOUBLE TANGENT TAND DOUBLE ARC SINE ASIND DOUBLE ARC COSINE ACOSD...
Page 593 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) • + ∞ • Not a number (NaN) −2.22507385850720×10 - 2.22507385850720×10 - −∞ +∞ −1 −1.79769313486232×10 1.79769313486232×10 The formats for NaN, ±∞ , and 0 are as follows: Special Numbers NaN*: e = 1,024 and f ≠...
Page 594 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Example 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 62 52 51...
Page 595 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Overflows, Underflows, Overflows will be output as either positive or negative infinity, depending on the sign of the result. Underflows will be output as either positive or negative and Illegal Calculations zero, depending on the sign of the result.
Page 596 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) • Ladder Program for the • Ladder Program for the Single-precision Calculation Double-precision Calculation 000000 000000 D00000 D00000 D00100 D00100 D01000 D01000 D01000 D01000 D00100 D00100 D00200 D00200 D01000 D01000 D01200 D01200...
Page 597 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) 1. This program section converts the BCD data 1. This program section converts the BCD data to single-precision floating-point data (32 bits, to double-precision floating-point data (64 IEEE754-format). bits, IEEE754-format). a) The BIN(023) instructions convert the a) The BIN(023) instructions convert the BCD data to binary and the FLT(452) in-...
Page 598 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) 3-16-1 DOUBLE FLOATING TO 16-BIT: FIXD(841) Purpose Converts a double-precision (64-bit) floating-point value to 16-bit signed binary data and places the result in the specified result word. This instruction is supported by the CS1-H, CJ1-H, CJ1M, and CS1D CPU Units only.
Page 599 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Description FIXD(841) converts the integer portion of the double-precision (64-bit) float- ing-point number in words S to S+3 (IEEE754-format) to 16-bit signed binary data and places the result in D. S+3CH S+2CH S+1CH...
Page 600 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Holding Bit Area H000 to H508 H000 to H510 Auxiliary Bit Area A000 to A956 A448 to A958 Timer Area T0000 to T4092 T0000 to T4094 Counter Area C0000 to C4092 C0000 to C4094 DM Area...
Page 601 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Precautions The content of words S to S+3 must be floating-point data and the integer por- tion must be in the range of –2,147,483,648 to 2,147,483,647. 3-16-3 16-BIT TO DOUBLE FLOATING: DBL(843) Purpose Converts a 16-bit signed binary value to double-precision (64-bit) floating- point data and places the result in the specified destination words.
Page 602 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 603 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications Area CIO Area CIO 0000 to CIO 6142 CIO 0000 to CIO 6140 Work Area W000 to W510 W000 to W508 Holding Bit Area...
Page 604 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag Equals Flag ON if both the exponent and mantissa of the result are 0. OFF in all other cases. Negative Flag ON if the result is negative. OFF in all other cases.
Page 605 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15...
Page 606 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the augend or addend data is not recognized as floating-point data. ON if the augend or addend data is not a number (NaN). ON if +∞...
Page 607 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area EM Area with bank En_00000 to En_32764 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767...
Page 608 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the minuend or subtrahend data is not recognized as floating-point data. ON if the minuend or subtrahend is not a number (NaN). ON if +∞...
Page 609 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area EM Area without bank E00000 to E32764 EM Area with bank En_00000 to En_32764 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C)
Page 610 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the multiplicand or multiplier data is not recognized as floating-point data. ON if the multiplicand or multiplier is not a number (NaN). ON if +∞...
Page 611 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area EM Area without bank E00000 to E32764 EM Area with bank En_00000 to En_32764 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C)
Page 612 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the dividend or divisor data is not recognized as floating-point data. ON if the dividend or divisor is not a number (NaN). ON if the dividend and divisor are both 0.
Page 613 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area EM Area with bank En_00000 to En_32764 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767...
Page 614 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Precautions The source data in words S to S+3 must be in IEEE754 floating-point data for- mat. 3-16-10 DOUBLE RADIANS TO DEGREES: DEGD(850) Purpose Converts a double-precision (64-bit) floating-point number from radians to degrees and places the result in the specified result words.
Page 615 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 616 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Ladder Symbol SIND(851) S: First source word D: First destination word Variations Variations Executed Each Cycle for ON Condition SIND(851) Executed Once for Upward Differentiation @SIND(851) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported.
Page 617 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Specify the desired angle (–65,535 to 65,535) in radians in words S to S+3. If the angle is outside of the range –65,535 to 65,535, an error will occur and the instruction won’t be executed.
Page 618 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Operand Specifications Area CIO Area CIO 0000 to CIO 6140 Work Area W000 to W508 Holding Bit Area H000 to H508 Auxiliary Bit Area A000 to A956 A448 to A956 Timer Area T0000 to T4092 Counter Area...
Page 619 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 65,535. OFF in all other cases. Equals Flag ON if both the exponent and mantissa of the result are 0.
Page 620 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767...
Page 621 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 65,535. OFF in all other cases. Equals Flag ON if both the exponent and mantissa of the result are 0.
Page 622 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area EM Area with bank En_00000 to En_32764 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767...
Page 623 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 1.0. OFF in all other cases.
Page 624 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area EM Area with bank En_00000 to En_32764 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767...
Page 625 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). ON if the absolute value of the source data exceeds 1.0. OFF in all other cases.
Page 626 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767...
Page 627 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). OFF in all other cases. Equals Flag ON if both the exponent and mantissa of the result are 0.
Page 628 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767...
Page 629 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not recognized as floating-point data. ON if the source data is negative. ON if the source data is not a number (NaN). OFF in all other cases.
Page 630 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767...
Page 631 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not recognized as floating-point data. ON if the source data is not a number (NaN). OFF in all other cases. Equals Flag ON if both the exponent and mantissa of the result are 0.
Page 632 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767...
Page 633 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Flags Name Label Operation Error Flag ON if the source data is not recognized as floating-point data. ON if the source data is negative. ON if the source data is not a number (NaN). OFF in all other cases.
Page 634 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area EM Area with bank En_00000 to En_32764 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767...
Page 635 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Name Label Operation Underflow Flag ON if the absolute value of the result is too small to be expressed as a double-precision floating-point value. Negative Flag ON if the result is negative. OFF in all other cases.
Page 636 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15...
Page 637 Section 3-16 Double-precision Floating-point Instructions (CS1-H, CJ1-H, CJ1M, or CS1D Only) Options With the three input types and six symbols, there are 18 different possible combinations. Symbol Option (data format) (Equal) D: Double-precision floating-point data < > (Not equal) < (Less than) <= (Less than or equal)
Page 638: Table Data Processing Instructions
Section 3-17 Table Data Processing Instructions Name Label Operation ON if C1 ≠ C2. Not Equal Flag OFF in all other cases. Less Than Flag < ON if C1 < C2. OFF in all other cases. ON if C1 ≤ C2. Less Than or <...
Page 639 Section 3-17 Table Data Processing Instructions Instruction Mnemonic Function code Page LAST IN FIRST OUT LIFO DIMENSION RECORD TABLE DIM SET RECORD LOCATION SETR GET RECORD NUMBER GETR DATA SEARCH SRCH SWAP BYTES SWAP FIND MAXIMUM FIND MINIMUM FRAME CHECKSUM STACK NUMBER OUTPUT SNUM STACK DATA READ...
Page 640 Section 3-17 Table Data Processing Instructions The following diagram shows the basic structure of a stack. PC memory Stack region Example Stack region address PC memory address of the last word in the stack Words in 16 words PC memory address of the stack region next data word (stack pointer) Pointer...
Page 641 Section 3-17 Table Data Processing Instructions LIFO(634) Reads the last (most recent) word of data that was stored in the stack. Decre- ments the pointer by one and reads the data at this address (the most recent data stored in the stack). The read data will not be cleared. Stack Stack Pointer...
Page 642 Section 3-17 Table Data Processing Instructions SWRIT(640) Writes the source data to the specified data element in the stack (overwriting the existing data). The offset value indicates the location of the desired word (the number of words before the current pointer position). Stack Stack Pointer to last...
Page 643 Section 3-17 Table Data Processing Instructions SDEL(642) Deletes the data element at the specified location in the stack and shifts the rest of the data in the stack upward. The offset value indicates the location of the desired word (the number of words before the current pointer position). Stack Stack Pointer to last...
Page 644 Section 3-17 Table Data Processing Instructions The following diagram shows the basic structure of a record table. Each record in a table has the same number of words. Table Record Same number of words Record in each record Record Index Registers (IR) can be used to indirectly reference table data. Address calculation of the record can be easily made by using the SETR(635) (SET RECORD NUMBER) instruction and GETR(636) (GET RECORD NUMBER).
Page 645 Section 3-17 Table Data Processing Instructions PC memory address of the last word in the stack (rightmost 4 digits) TB+1 PC memory address of the last word in the stack (leftmost 4 digits) TB+2 Stack pointer (rightmost 4 digits) TB+3 Stack pointer (leftmost 4 digits) TB+4 through TB+(N–1): Data storage region The remainder of the stack is used to store data.
Page 646 Section 3-17 Table Data Processing Instructions Area Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 647 Section 3-17 Table Data Processing Instructions &10 PC memory address PC memory address of last word in stack Stack pointer Last word in stack 10 words Stack pointer 3-17-2 PUSH ONTO STACK: PUSH(632) Purpose Writes one word of data to the specified stack. Ladder Symbol PUSH(632) TB: First stack address...
Page 648 Section 3-17 Table Data Processing Instructions PC memory address of the last word in the stack (rightmost 4 digits) TB+1 PC memory address of the last word in the stack (leftmost 4 digits) TB+2 Stack pointer (rightmost 4 digits) TB+3 Stack pointer (leftmost 4 digits) TB+4 through TB+(N–1): Data storage region The remainder of the stack is used to store data.
Page 649 Section 3-17 Table Data Processing Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description PUSH(632) writes the content of S to the address indicated by the stack pointer (TB+3 and TB+2) and increments the stack pointer by one.
Page 650 Section 3-17 Table Data Processing Instructions Examples When CIO 000000 is ON in the following example, PUSH(632) copies the content of D00200 to the stack beginning at D00000. In this case, the stack pointer indicates D00007. PC memory address PC memory address of last word in stack Stack pointer Stack...
Page 651 Section 3-17 Table Data Processing Instructions Operands TB through TB+3: Stack control words The first four words of the stack contain the PLC memory address of the last word in the stack and the stack pointer (the PLC memory address of the next word to be overwritten by PUSH(632)).
Page 652 Section 3-17 Table Data Processing Instructions Area Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 653 Section 3-17 Table Data Processing Instructions Examples When CIO 000000 is ON in the following example, FIFO(633) reads the con- tent of D00004 (TB+4 for the stack beginning at D00000) and writes that data to D00300. PC memory address of last word in stack Stack pointer Last word Stack...
Page 654 Section 3-17 Table Data Processing Instructions Operands TB through TB+3: Stack control words The first four words of the stack contain the PLC memory address of the last word in the stack and the stack pointer (the PLC memory address of the next word to be overwritten by PUSH(632)).
Page 655 Section 3-17 Table Data Processing Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description LIFO(634) reads the data from the address indicated by the stack pointer (the newest word of data in the stack), decrements the stack pointer by one, and...
Page 656 Section 3-17 Table Data Processing Instructions Examples When CIO 000000 is ON in the following example, LIFO(634) reads the con- tent of the word indicated by the stack pointer (D00006) and writes that data to D00300. PC memory address of last word in stack Stack pointer Stack Last word...
Page 657 Section 3-17 Table Data Processing Instructions Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands N: Table number Indicates the table number. N must be between 0 and15. LR: Length of each record Indicates the number of words in each record. LR must be 0001 to FFFF hexadecimal (1 to 65,535 words).
Page 658 Section 3-17 Table Data Processing Instructions addresses in data tables. Use DIM(631) to divide data into records and then use SETR(635) to store the first address of the desired record in an Index Register. The Index Register can then be used as a pointer in other instruc- tions, such as read, write, search, or compare instructions.
Page 659 Section 3-17 Table Data Processing Instructions 3-17-6 SET RECORD LOCATION: SETR(635) Purpose Writes the location of the specified record (the PLC memory address of the beginning of the record) in the specified Index Register. Ladder Symbol SETR(635) N: Table number R: Record number D: Destination Index Register Variations...
Page 660 Section 3-17 Table Data Processing Instructions Area Index Registers IR0 to IR15 Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,– (– –)IR0 to, – (– –)IR15 Description SETR(635) stores the PLC memory address of the first word of the specified record in the specified Index Register.
Page 661 Section 3-17 Table Data Processing Instructions 3-17-7 GET RECORD NUMBER: GETR(636) Purpose Returns the record number of the record at the PLC memory address con- tained in the specified Index Register. Ladder Symbol GETR(636) N: Table number IR: Index Register D: Destination word Variations Variations...
Page 662 Section 3-17 Table Data Processing Instructions Area Index Registers IR0 to IR15 Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description GETR(636) finds which record includes the PLC memory address contained in the specified Index Register and writes that record number in D.
Page 663 Section 3-17 Table Data Processing Instructions 3-17-8 DATA SEARCH: SRCH(181) Purpose Searches for a word of data within a range of words. In CS1-H, CJ1-H, and CJ1M CPU Units, this instruction can be run in the background. Refer to the CS/CJ Series Programmable Controllers Program- ming Manual for details on background execution.
Page 664 Section 3-17 Table Data Processing Instructions Operand Specifications Area CIO Area CIO 0000 to CIO 0000 to CIO 6143 CIO 6142 Work Area W000 to W510 W000 to W511 Holding Bit Area H000 to H510 H000 to H511 Auxiliary Bit Area A000 to A958 A000 to A959 Timer Area...
Page 665 Section 3-17 Table Data Processing Instructions SRCH(181) searches table data that contains one word in each record. For searching data that contains more than one word per record, use DIM(631), SETR(635), GETR(636), FOR(512)–NEXT(513), or BREAK(514) together with an Index Register (IR). The status of the Equals Flag can be checked immediately after execution to determine whether or not there was a match.
Page 666 Section 3-17 Table Data Processing Instructions Variations Variations Executed Each Cycle for ON Condition SWAP(637) Executed Once for Upward Differentiation @SWAP(637) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 667 Section 3-17 Table Data Processing Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description SWAP(637) switches the position of the two bytes in all of the words in the range of memory from R1 to R1+N–1.
Page 668 Section 3-17 Table Data Processing Instructions Variations Variations Executed Each Cycle for ON Condition MAX(182) Executed Once for Upward Differentiation @MAX(182) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 669 Section 3-17 Table Data Processing Instructions Operand Specifications Area CIO Area CIO 0000 to CIO 0000 to CIO 6143 CIO 6142 Work Area W000 to W510 W000 to W511 Holding Bit Area H000 to H510 H000 to H511 Auxiliary Bit Area A000 to A958 A000 to A959 A448 to A959...
Page 670 Section 3-17 Table Data Processing Instructions Flags Name Label Operation Error Flag ON if the content of C isn’t within the specified range of 0001 through FFFF. OFF in all other cases. Equals Flag ON if the maximum value is 0000. OFF in all other cases.
Page 671 Section 3-17 Table Data Processing Instructions 3-17-11 FIND MINIMUM: MIN(183) Purpose Finds the minimum value in the range. In CS1-H, CJ1-H, and CJ1M CPU Units, this instruction can be run in the background. Refer to the CS/CJ Series Programmable Controllers Program- ming Manual for details on background execution.
Page 672 Section 3-17 Table Data Processing Instructions Data type Index Register output 8000 Signed binary C000 Signed binary R1: First word in range R1 specifies the first word in the search range. The words from R1 to R1+(C– 1) are searched for the minimum value. (C is the number of words specified in Search range R1+(C–1) Note R1 and R1+C–1 must be in the same data area.
Page 673 Section 3-17 Table Data Processing Instructions Description MIN(183) searches the range of memory from R1 to R1+C–1 for the minimum value in the range and outputs that minimum value to D. When bit 14 of C+1 has been set to 1, MIN(183) writes the PLC memory address of the word containing the minimum value to IR00.
Page 674 Section 3-17 Table Data Processing Instructions C: D00100 10 words Number of words C+1: D00101 Always 0. 1: Outputs address to IR00. 1: Treats data as signed binary. Decimal equivalent –2 PC memory address –1 Min. value 100CF –3 D: D00300 000100CF 3-17-12 SUM: SUM(184) Purpose...
Page 675 Section 3-17 Table Data Processing Instructions Operands C and C+1: Control words C specifies the number of units (bytes or words) to be summed. (Bit 13 of C+1 determines whether bytes or words are being summed.) Bits 12 to 15 of C+1 indicate what type of data is being summed, as shown in the following diagram.
Page 676 Section 3-17 Table Data Processing Instructions Area EM Area without bank E00000 to E00000 to E00000 to E32766 E32767 E32766 EM Area with bank En_00000 to En_00000 to En_00000 to En_32766 En_32767 En_32766 (n = 0 to C) (n= 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767...
Page 677 Section 3-17 Table Data Processing Instructions Examples When CIO 000000 is ON in the following example, SUM(184) adds 10 bytes of unsigned binary data beginning with the rightmost byte of D00100 and writes the result to D00201 and D00200. Number of words/bytes C+1: D00301 Always 0.
Page 678 Section 3-17 Table Data Processing Instructions Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands C and C+1: Control words C specifies the number of units (bytes or words) to be used in the FCS calcu- lation.
Page 679 Section 3-17 Table Data Processing Instructions Area Counter Area C0000 to C4094 C0000 to C4095 DM Area D00000 to D00000 to D32767 D32766 EM Area without bank E00000 to E00000 to E32767 E32766 EM Area with bank En_00000 to En_0000 to En_32767 En_32766 (n = 0 to C) (n = 0 to C)
Page 680 Section 3-17 Table Data Processing Instructions Examples When CIO 000000 is ON in the following example, FCS(180) calculates the FCS value for the 10 bytes of data beginning with the rightmost byte of D00100 and writes the result to D00200. C+1: D00301 Always 0.
Page 681 Section 3-17 Table Data Processing Instructions Operands TB through TB+3: Stack control words The first four words of the stack contain the PLC memory address of the last word in the stack and the stack pointer (the PLC memory address of the next available word in the stack.) PLC memory address of the last word in the stack (rightmost 4 digits)
Page 682 Section 3-17 Table Data Processing Instructions Area Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 683 Section 3-17 Table Data Processing Instructions 3-17-15 STACK DATA READ: SREAD(639) Purpose Reads the data from the specified data element in the stack. The offset value indicates the location of the desired data element (how many data elements before the current pointer position). This instruction is supported by the CS1-H, CJ1-H, CJ1M, and CS1D CPU Units only.
Page 684 Section 3-17 Table Data Processing Instructions TB+4 through TB+(N–1): Data storage region The remainder of the stack is used to store data. TB+4 Data storage region TB+(N–1) Operand Specifications Area CIO Area CIO 0000 to CIO 6143 Work Area W000 to W511 Holding Bit Area H000 to H511 Auxiliary Bit Area...
Page 685 Section 3-17 Table Data Processing Instructions PLC memory Stack address TB+1 TB+2 TB+3 TB+4 The data (A) is Pointer not changed. Offset value Last word in stack Reads the data (A) without changing the stack pointer. Reads the data (A) in the specified word and outputs that data to D.
Page 686 Section 3-17 Table Data Processing Instructions 000000 SREAD D00000 PLC memory &3 address D00100 PLC memory address D00000 of last word in the D00001 D00002 Stack pointer D00003 D00004 Stack pointer D00005 −3 Last word D00006 D00100 in stack D00007 D00008 D00009 D00000...
Page 687 Section 3-17 Table Data Processing Instructions Operands TB through TB+3: Stack control words The first four words of the stack contain the PLC memory address of the last word in the stack and the stack pointer (the PLC memory address of the next available word in the stack.) PLC memory address of the last word in the stack (rightmost 4 digits)
Page 688 Section 3-17 Table Data Processing Instructions Area Constants #0001 to #FFFB #0000 to #FFFF (Hexadecimal) (Hexadecimal) Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 689 Section 3-17 Table Data Processing Instructions case, the stack pointer indicates D00007 and the offset value is 3, so the data in D00004 is overwritten. 000000 SWRIT D00000 &3 PLC memory address D00100 D00000 PLC memory address of last word in the stack D00001 (Overwrite) D00002...
Page 690 Section 3-17 Table Data Processing Instructions Operands TB through TB+3: Stack control words The first four words of the stack contain the PLC memory address of the last word in the stack and the stack pointer (the PLC memory address of the next available word in the stack.) PLC memory address of the last word in the stack (rightmost 4 digits)
Page 691 Section 3-17 Table Data Processing Instructions Area Constants #0001 to #FFFB #0000 to #FFFF (Hexadecimal) (Hexadecimal) Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 692 Section 3-17 Table Data Processing Instructions Examples When CIO 000000 is ON in the following example, SINS(641) inserts the source data in D00100 at the specified address in the stack starting at D00000. In this case, the stack pointer indicates D00007 and the offset value is 3, so the source data is inserted in D00004.
Page 693 Section 3-17 Table Data Processing Instructions Variations Variations Executed Each Cycle for ON Condition SDEL(642) Executed Once for Upward Differentiation @SDEL(642) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 694 Section 3-17 Table Data Processing Instructions Area EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD...
Page 695 Section 3-17 Table Data Processing Instructions Flags Name Label Operation Error Flag ON if the content of the stack pointer (TB+3 and TB+2) is less than or equal to the PLC memory address of first word in the data region of the stack (TB+4). (This is a stack underflow error.) ON if the offset value specified in C is 0 or greater than the maximum data region size (FFFB Hex).
Page 696: Data Control Instructions
Data Control Instructions Section 3-18 3-18 Data Control Instructions 3-18-1 PID CONTROL: PID(190) Purpose Executes PID control according to the specified parameters. Ladder Symbol PID(190) S: Input word C: First parameter word D: Output word Variations Variations Executed Each Cycle for ON Condition PID(190) Executed Once for Upward Differentiation Not supported.
Page 697 Data Control Instructions Section 3-18 Operand Specifications Area CIO Area CIO 0000 to CIO CIO 0000 to CIO 0000 to CIO 6143 CIO 6105 6143 Work Area W000 to W511 W000 to W473 W000 to W511 Holding Bit Area H000 to H511 H000 to H473 H000 to H511 Auxiliary Bit Area...
Page 698 Data Control Instructions Section 3-18 Parameters (C to C+8) PID control PV input (S) Manipulated variable (D) The number of valid input data bits within the 16 bits of the PV input (S) is designated by the input range setting in C+6, bits 08 to 11. For example, if 12 bits (4 hex) is designated for the input range, the range from 0000 hex to 0FFF hex will be enabled as the PV.
Page 699 Data Control Instructions Section 3-18 Flags Name Label Operation Error Flag ON if the C data is out of range. ON if the actual sampling period is more than twice the designated sampling period. OFF in all other cases. Greater Than >...
Page 700 Data Control Instructions Section 3-18 Set value: 300 C: D00200 Proportional band: 10.0% C+1: D00201 Integral time: 120.0 s C+2: D00202 Derivative time: 40.0 s C+3: D00203 Sampling period: 0.5 s Parameters C+4: D00204 Reverse operation (bit 00: 0) /PID constant updating timing=input condition C+5: D00205 is ON (bit 01: 0)/ set value = manipulated variable output 50% (bit 03: 1) / C+6: D00206...
Page 701 Data Control Instructions Section 3-18 From Analog Input Unit Execution condition Control Data C (D01000): 0000 Hex (binary with one table) D01000 C+1 (D01001): 1770 Hex (Xm) C+2 (D01002): 0000 Hex (Yo) Analog input value C+3 (D01003): 1770 Hex (X1) C+4 (D01004): FFFF Hex (Y1) D02000 Control Data...
Page 702 Data Control Instructions Section 3-18 Simple PID Control Feed-forward PID Control As the target response is slowed, Target response Disturbance response the disturbance response worsens. As the disturbance response is Overshoot slowed, the target response worsens. PID Parameter Settings Control Item Contents Setting range...
Page 703 Data Control Instructions Section 3-18 Control Item Contents Setting range Change with data ON input condition Bit 00 of C+5 PID forward/reverse Determines the direction of the 0: Reverse action Not allowed designation proportional action. 1: Forward action Bit 12 of C+6 Manipulated vari- Determines whether or not limit 0: Disabled (no limit control) able output limit...
Page 704 Data Control Instructions Section 3-18 cycle, the 80 ms is added to 60 ms. Because the sum of 140 ms is greater than 100 ms, PID(190) will be executed and the surplus of 40 ms (i.e., 120 ms – 100 ms = 20 ms) will be carried forward. This procedure is re- peated for subsequent cycles.
Page 705 Data Control Instructions Section 3-18 time, the stronger the correction by the integral action will be. If the integral time is too short, the correction will be too strong and will cause hunting to occur. Integral Action Step response Deviation Manipulated variable Pi Action and Integral Time...
Page 706 Data Control Instructions Section 3-18 hunting, integral action to automatically correct any offset, and derivative action to speed up the response to disturbances. Step Response of PID Control Action Output Step response Deviation PID action I action P action Manipulated D action variable Ramp Response of PID Control Action Output...
Page 707 Data Control Instructions Section 3-18 When P is narrowed Control by measured PID • When there is broad hunting, or when operation is tied up by overshooting and undershooting, it is probably because integral action is too strong. The hunting will be reduced if the integral time is increased or the propor- tional band is enlarged.
Page 708 Data Control Instructions Section 3-18 Parameters The following diagrams show the locations of the parameter data. For details on the parameters, refer to PID Parameter Settings in this section. Set value (SV) Proportional band (P) Integral constant (Tik) Derivative constant (Tdk) Sampling period ( τ) 3 2 1 Forward/reverse designation...
Page 709 Data Control Instructions Section 3-18 Area EM Area with bank En_00000 to En_00000 to En_00000 to En_32767 En_32729 En_32767 (n = 0 to C) (n = 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 710 Data Control Instructions Section 3-18 and the new P, I, and D constants are stored automatically in C+1, C+2, and C+3. At this point, the AT Command Bit (bit 15 of C+9) is turned OFF and PID control resumes with the new PID constants in C+1, C+2, and C+3. •...
Page 711 Data Control Instructions Section 3-18 The direction of proportional operation can be designated as either forward or reverse. The upper and lower limits of the manipulated variable output can be desig- nated. The sampling period can be designated in units of 10 ms (0.01 to 99.99 s), but the actual PID action is determined by a combination of the sampling period and the time of PIDAT(191) instruction execution (with each cycle).
Page 712 Data Control Instructions Section 3-18 Precautions PIDAT(191) is executed as if the execution condition was a STOP-RUN signal. PID calculations are executed when the execution condition remains ON for the next cycle after C+11 to C+40 are initialized. Therefore, when using the Always ON Flag (ON) as an execution condition for PIDAT(191), provide a separate process where C+11 to C+40 are initialized when operation is started.
Page 713 Data Control Instructions Section 3-18 Control Item Contents Setting range Change with data ON input condition Bit 00 of C+5 PID forward/reverse Determines the direction of the 0: Reverse action Not allowed designation proportional action. 1: Forward action Bit 12 of C+6 Manipulated vari- Determines whether or not limit 0: Disabled (no limit control) able output limit...
Page 714 Data Control Instructions Section 3-18 Note 1. When the unit is designated as 1, the range is from 1 to 8,191 times the period. When the unit is designated as 9, the range is from 0.1 to 819.1 s. When 9 is designated, set the integral and derivative times to within a range of 1 to 8,191 times the sampling period.
Page 715 Data Control Instructions Section 3-18 Calculated PID PID control starts. constants are set. CIO 000000 PID control PID control AT executing W000000 Bit 15 of D00209 Time Time...
Page 716 Data Control Instructions Section 3-18 Example 2: At the rising edge of CIO 000000 (OFF to ON), autotuning will be performed first if bit 15 of D00209 (C+9) is ON. When autotuning is completed, the calcu- Starting PIDAT(191) with Autotuning lated P, I, and D constants are written to C+1, C+2, and C+3.
Page 717 Data Control Instructions Section 3-18 3-18-3 LIMIT CONTROL: LMT(680) Purpose Controls output data according to whether or not input data is within upper and lower limits. Ladder Symbol LMT(680) S: Input word C: First limit word D: Output word Variations Variations Executed Each Cycle for ON Condition LMT(680)
Page 718 Data Control Instructions Section 3-18 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description When the execution condition is ON, LMT(680) controls output data according to whether or not the specified input data (signed 16-bit binary) is within the upper and lower limits.
Page 719 Data Control Instructions Section 3-18 Precautions If the upper limit is less than the lower limit, an error will occur and the Error Flag will turn ON. If the input data (S) is greater than the upper limit, the Greater Than Flag will turn ON.
Page 720 Data Control Instructions Section 3-18 Variations Variations Executed Each Cycle for ON Condition BAND(681) Executed Once for Upward Differentiation @BAND(681) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operand Specifications...
Page 721 Data Control Instructions Section 3-18 If the input data (S) is greater than or equal to the lower limit (C) and less than or equal to the upper limit (C+1), 0000 (hex) will be output to D and the Equals Flag will turn ON.
Page 722 Data Control Instructions Section 3-18 Lower limit: 200 Upper limit: 300 Lower limit Lower Upper limit: limit: Upper limit 3-18-5 DEAD ZONE CONTROL: ZONE(682) Purpose Adds the specified bias to input data and outputs the result. Ladder Symbol ZONE(682) S: Input word C: First limit word D: Output word Variations...
Page 723 Data Control Instructions Section 3-18 Area EM Area with bank En_00000 to En_00000 to En_00000 to En_32767 En_32766 En_32767 (n = 0 to C) (n = 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 724 Data Control Instructions Section 3-18 Flags Name Label Operation Error Flag ON if the upper limit is less than the lower limit. OFF in all other cases. Greater Than > ON if the input data (S) is greater than the upper limit. Flag OFF in all other cases.
Page 725 Data Control Instructions Section 3-18 3-18-6 SCALING: SCL(194) Purpose Converts unsigned binary data into unsigned BCD data according to the specified linear function. Ladder Symbol SCL(194) S: Source word P1: First parameter word R: Result word Variations Variations Executed Each Cycle for ON Condition SCL(194) Executed Once for Upward Differentiation @SCL(194)
Page 726 Data Control Instructions Section 3-18 Area Timer Area T0000 to T4095 T0000 to T4092 T0000 to T4095 Counter Area C0000 to C4095 C0000 to C4092 C0000 to C4095 DM Area D00000 to D00000 to D00000 to D32767 D32764 D32767 EM Area without bank E00000 to E00000 to E00000 to...
Page 727 Data Control Instructions Section 3-18 R (unsigned BCD) Scaling is performed according to the linear function defined by points A and B. (BCD) Point B Converted value P1+1 (BIN) Point A (BCD) P1+2 Converted value P1+3 (BIN) S (unsigned binary) SCL(194) can be used to scale the results of analog signal conversion values from Analog Input Units according to user-defined scale parameters.
Page 728 Data Control Instructions Section 3-18 Contents of D00200 (R) (BCD) D00100 (BIN) P1+1: D00101 Point B (BCD) P1+2: D00102 (BIN) P1+3: D00103 Point A Contents of CIO 0200 (S) Negative Values An Analog Input Unit actually inputs values from FF38 to 1068 hexadecimal for 0.8 to 5.2 V.
Page 729 Data Control Instructions Section 3-18 Reverse Scaling Reverse scaling can also be used by setting As < Bs and Ar > Br. The follow- ing relationship will result. R (unsigned BCD) Point A Point B S (unsigned binary) Reverse scaling can be used, for example, to convert (reverse scale) 1 to 5 V (0000 to 0FA0 hexadecimal) to 0300 to 0000, respectively, as shown in the fol- lowing diagram.
Page 730 Data Control Instructions Section 3-18 Operands The contents of the three words starting with the first parameter word (P1) are shown in the following diagram. Offset of linear function 8000 to 7FFF (signed binary) P1+1 ∆X 8000 to 7FFF (signed binary) P1+2 ∆Y 0000 to 9999 (BCD)
Page 731 Data Control Instructions Section 3-18 Description SCL2(486) is used to convert the signed binary data contained in the source word S into signed BCD data (the BCD data contains the absolute value and the Carry Flag shows the sign) and place the result in the result word R according to the linear function defined by the slope ( ∆...
Page 732 Section 3-18 Data Control Instructions Flags Name Label Operation Error Flag ON if the contents of C+1 (∆X) is 0000. ON if the contents of C+2 (∆Y) is not BCD. OFF in all other cases. Equals Flag ON if the result is 0. OFF in all other cases.
Page 733 Section 3-18 Data Control Instructions When CIO 000000 is ON, the contents of CIO 2005 is scaled using the linear function defined by ∆ X (0FA0), ∆ Y (0400), and the offset (07D0). These values are contained in D00100 to D00102, and the result is output to D00200. Contents of R (D00200) Offset D00100...
Page 734 Data Control Instructions Section 3-18 Operands The contents of the five words starting with the first parameter word (P1) are shown in the following diagram. Offset of linear function 8000 to 7FFF (signed binary) P1+1 ∆X 0001 to 9999 (BCD) P1+2 ∆Y 8000 to 7FFF (signed binary)
Page 735 Section 3-18 Data Control Instructions Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Data Registers DR0 to DR15 DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15...
Page 736 Data Control Instructions Section 3-18 Negative Offset Positive Offset R (signed binary) R (signed binary) Max conversion Max conversion ∆Y ∆Y ∆X ∆X Offset S (signed BCD) Min. conversion Offset S (signed BCD) Min. conversion Offset of 0000 R (signed binary) Max conversion ∆Y ∆X...
Page 737 Data Control Instructions Section 3-18 Offset Contents of R (2011, signed binary) ∆X P1+1: ∆Y P1+2: P1+3: Max. conversion P1+4: Min. conversion ∆Y (0FA0 Hex) Contents of S (D00000, signed BCD) ∆X (0200) 3-18-9 AVERAGE: AVG(195) Purpose Calculates the average value of an input word for the specified number of cycles.
Page 738 Section 3-18 Data Control Instructions Average R+1: Processing information Used by system. Average Valid Flag OFF: Not valid (AVG(195) has not yet been executed the specified number of cycles.) Valid. R+2: Previous value #1 Previous value #N R+N+1: Note R to R+N+1 must be in the same area. Operand Specifications Area CIO Area...
Page 739 Data Control Instructions Section 3-18 turned ON. For all further cycles, the value in R will be updated for the most current N values of S. The maximum value of N is 64. The Previous Value Pointer will be reset to 0 after N–1 values have been writ- ten.
Page 740 Data Control Instructions Section 3-18 S: D00100 N: D00200 (10 times) R: CIO 0300 Pointer R+1: CIO 0301 Average Valid Flag Average S, scan 1 R+2: CIO 0302 S, scan 2 R+3: CIO 0303 S, scan n R+11: CIO 0311 Examples In the following example, the content of CIO 0040 is set to #0000 and then incremented by 1 each cycle.
Page 741: Subroutines
Subroutines Section 3-19 3-19 Subroutines 3-19-1 SUBROUTINE CALL: SBS(091) Purpose Calls the subroutine with the specified subroutine number and executes that program. Ladder Symbol SBS(091) N: Subroutine number Variations Variations Executed Each Cycle for ON Condition SBS(091) Executed Once for Upward Differentiation @SBS(091) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification...
Page 742 Section 3-19 Subroutines Execution condition ON Main program Subroutine program (SBN(092) to RET(093)) Program end Subroutines can be nested up to 16 levels. Nesting is when another subrou- tine is called from within a subroutine program, such as shown in the following example, which is nested to 3 levels.
Page 743 Section 3-19 Subroutines Note A subroutine can be called more than once in a program. Subroutines and Observe the following precautions when using differentiated instructions Differentiation (DIFU(013), DIFU(014), or up/down differentiated instructions) in subroutines. The operation of differentiated instructions in a subroutine is unpredictable if a subroutine is executed more than once in the same cycle.
Page 744 Subroutines Section 3-19 Flags Name Label Operation Error Flag ON if nesting exceeds 16 levels. ON if the specified subroutine number doesn’t exist. ON if a subroutine calls itself. ON if a subroutine being executed is called. ON if the specified subroutine isn’t defined in the current task.
Page 745 Section 3-19 Subroutines CIO 000000 ON Main program CIO 000001 ON Order of execution A→S1→B→S2→C A→S1→B→C A→B→S2→C A→B→C Subroutines Program end Example 3: Nested Subroutines When CIO 000000 is ON in the following example, subroutine 1 is executed. If CIO 000001 is ON, subroutine 2 is executed from within subroutine 1 and program execution returns to the next instruction after SBS(091) 2 when sub- routine 2 is completed.
Page 746 Subroutines Section 3-19 CIO 000000 ON Order of execution A→S1-1→S2→S1-2→B Subroutine 1 A→S1-1→S1-2→B CIO 000001 ON A→B A→B Subroutine 2 3-19-2 MACRO: MCRO(099) Purpose Calls the subroutine with the specified subroutine number and executes that program using the input parameters in S to S+3 and the output parameters in D to D+3.
Page 747 Subroutines Section 3-19 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands N: Subroutine number Specifies the subroutine number between 0 and 1023 decimal. Operand Specifications Area CIO Area CIO 0000 to CIO 6140 Work Area W000 to W508 Holding Bit Area H000 to H508...
Page 748 Section 3-19 Subroutines MCRO(099) Execution of subrou- tine between SBN(092) and RET(093). MCRO(099) The subroutine uses A600 to A603 as inputs and A604 to A607 as outputs. MCRO(099) can be used to consolidate two or more subroutines with the same structure but different input and output addresses into a single subrou- tine program.
Page 749 Subroutines Section 3-19 2. The second MCRO(099) instruction passes the input data in CIO 0200 to CIO 0203 and executes the subroutine. When the subroutine is complet- ed, the output data is stored in CIO 0400 to CIO 0403. Input data is passed when the subroutine is called.
Page 750 Subroutines Section 3-19 3-19-3 SUBROUTINE ENTRY: SBN(092) Purpose Indicates the beginning of the subroutine program with the specified subrou- tine number. Used in combination with RET(093) to define a subroutine region. Ladder Symbol SBN(092) N: Subroutine number Variations Variations Executed Each Cycle for ON Condition SBN(092) Immediate Refreshing Specification Not supported...
Page 751 Subroutines Section 3-19 MCRO Subroutine region Precautions When the subroutine isn’t being executed, the instructions are treated as NOP(000). Place the subroutines after the main program and just before the END(001) instruction in the program for each task. If part of the main program is placed after the subroutine region, that program section will be ignored.
Page 752 Subroutines Section 3-19 Not allowed Task 1 Task Task 2 The step instructions, STEP(008) and SNXT(009) cannot be used in subrou- tines. Not allowed Example When CIO 000000 is ON in the following example, subroutine 10 is executed and program execution returns to the next instruction after the SBS(091) or MCRO(099) instruction that called the subroutine.
Page 753 Subroutines Section 3-19 3-19-4 SUBROUTINE RETURN: RET(093) Purpose Indicates the end of a subroutine program. Used in combination with SBN(092) to define a subroutine region. Ladder Symbol RET(093) Variations Variations Executed Each Cycle for ON Condition RET(093) Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas...
Page 754 Subroutines Section 3-19 Operands N: Global subroutine number Specifies the global subroutine number between 0 and 1023 decimal. Operand Specifications Area CIO Area Work Area Holding Bit Area Auxiliary Bit Area Timer Area Counter Area DM Area EM Area without bank EM Area with bank Indirect DM/EM addresses in binary...
Page 755 Subroutines Section 3-19 Execution Execution Cyclic or interrupt task Cyclic or interrupt task condition ON condition ON 000000 000001 GSBS GSBS Main program Interrupt task 0 GSBN Global subroutine program (GSBN(751) to GRET(752)) GRET Multiple global subroutine regions (GSBN(751) to GRET(752)) can be defined in interrupt task 0.
Page 756 Subroutines Section 3-19 Cyclic or interrupt task Execution condition ON 000000 GSBS Execution 000001 condition ON GSBS Interrupt task 0 GSBN GRET Subroutine functions GSBN divided by task. GRET An SBS(091) or GSBS(750) instruction can be written within a subroutine region (SBN(092) to RET(093)) or global subroutine region (GSBN(751) to GRET(752)) to “nest”...
Page 757 Subroutines Section 3-19 from OFF to ON. If CIO 000001 is ON in the same cycle, global subroutine 0001 will be executed again but this time DIFU(013) will not detect the rising edge of CIO 000001 and CIO 000100 will be turned OFF. Cyclic task 1 000000 GSBS...
Page 758 Subroutines Section 3-19 Cyclic task 1 000000 GSBS Interrupt task 0 The subroutine is not executed in following cycles. GSBN 000001 DIFU 000100 GRET Flags Name Label Operation Error Flag ON if nesting exceeds 16 levels (counting both regular and global subroutines). ON if the specified global subroutine doesn’t exist.
Page 759 Subroutines Section 3-19 Examples Example 1 When CIO 000000 is ON in the following example, global subroutine 1 is exe- cuted and program execution returns to the next instruction after GSBS(750). Status of CIO 000000 Order of program execution A → S → B A →...
Page 760 Subroutines Section 3-19 When CIO 000000 is ON, global subroutine program 1 is executed. When CIO 000001 is ON, global subroutine program 2 is executed. Cyclic or interrupt task 000000 GSBS CIO 000000 ON 000001 CIO 000001 CIO 000001 ON GSBS Subroutine program It is possible to debug problems...
Page 761 Subroutines Section 3-19 3-19-6 GLOBAL SUBROUTINE ENTRY: GSBN(751) Purpose Indicates the beginning of the global subroutine program with the specified subroutine number. Used in combination with GRET(752) to define a global subroutine region. This instruction is supported by the CS1-H, CJ1-H, CJ1M, and CS1D CPU Units only.
Page 762 Section 3-19 Subroutines and the Error Flag will be turned ON when the GSBS(750) instruction is exe- cuted. The GSBS(750) instruction can be written both cyclic tasks (including extra cyclic tasks) and interrupt tasks. Cyclic or interrupt task GSBS Interrupt task 0 GSBN Global subroutine...
Page 763 Section 3-19 Subroutines • Always place the global subroutines in interrupt task 0. An error will occur if a global subroutine is called and the subroutine is not in interrupt task 0. Not allowed Cyclic task 1 Cyclic task 1 GSBS GSBS Cyclic task 2...
Page 764 Subroutines Section 3-19 Example When CIO 000000 is ON in the following example, global subroutine 10 is executed and program execution returns to the next instruction after the GSBS(750) instruction that called the subroutine. Cyclic or interrupt task 000000 GSBS Interrupt task 0 GSBN Global subroutine...
Page 765: Interrupt Control Instructions
Section 3-20 Interrupt Control Instructions 3-20 Interrupt Control Instructions 3-20-1 SET INTERRUPT MASK: MSKS(690) Purpose Both I/O interrupt tasks and scheduled interrupt tasks are masked (disabled) when the PLC enters RUN mode. MSKS(690) can be used to unmask or mask I/O interrupts and set the time intervals for scheduled interrupts. MSKS(690) is not supported by the CS1D CPU Units.
Page 766 Interrupt Control Instructions Section 3-20 Specifying I/O Interrupt Processing Rising/Falling Edge Designation Operand Contents Specify the Interrupt Input Unit’s unit number. 2: Unit number 0 3: Unit number 1 Specify either the rising or falling edge of the interrupt input sig- nal.
Page 767 Interrupt Control Instructions Section 3-20 CJ1M CPU Unit Built-in Interrupt Inputs Specifying I/O Interrupt Processing and Mask Processing Operand Contents Specify the interrupt input number. 6: Interrupt input 0 7: Interrupt input 1 8: Interrupt input 2 9: Interrupt input 3 Interrupt mask.
Page 768 Section 3-20 Interrupt Control Instructions Specifying Scheduled Interrupts Operand Contents Specify the scheduled interrupt number. 4: Interrupt task 2 5: Interrupt task 3 0000: Disable scheduled interrupt. 0001 to 270F Hex: Scheduled interrupt interval (1 to 9999) Note The unit for the scheduled interrupt interval can be set to either 10 ms or 1.0 ms in the PLC Setup interrupt settings.
Page 769 Interrupt Control Instructions Section 3-20 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –) IR0 to, –(– –) IR15 Description MSKS(690) controls I/O interrupts and scheduled interrupts.
Page 770 Interrupt Control Instructions Section 3-20 Flags Name Label Operation Error Flag ON if N isn’t within the specified range of 0 to 5 (0 to 15 for CJ1M Built-in Interrupt Inputs). ON if S isn’t within the specified range of 0000 to 00FF hex when N is 0 to 3 (when using a C200HS-INT01 and specifying I/O Interrupt Processing).
Page 771 Interrupt Control Instructions Section 3-20 in the PLC Setup. If cyclic refreshing with the Special I/O Unit isn’t disabled, IORF(097) might be executed during cyclic refreshing resulting in a non-fatal Duplicate Refresh Error and turning ON the Interrupt Task Error Flag (A40213).
Page 772 Interrupt Control Instructions Section 3-20 Variations Variations Executed Each Cycle for ON Condition MSKR(692) Executed Once for Upward Differentiation @MSKR(692) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 773 Interrupt Control Instructions Section 3-20 C200HS-INT01 Reading Masks Operand Contents Specify the Interrupt Input Unit’s unit number. 0: Unit number 0 1: Unit number 1 2: Unit number 2 3: Unit number 3 Interrupt mask status. 0000 to 00FF Hex (8 bits per Unit) Individual bits indicate the following: 0: Interrupt enabled 1: Interrupt masked...
Page 774: Area N
Interrupt Control Instructions Section 3-20 Reading I/O Interrupt Processing Rising/Falling Edge Designation Operand Contents Specify the interrupt input number. 10: Interrupt input 0 11: Interrupt input 1 12: Interrupt input 2 13: Interrupt input 3 Specify either the rising or falling edge of the interrupt input sig- nal.
Page 775: Dm Area
Interrupt Control Instructions Section 3-20 Area DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 776 Interrupt Control Instructions Section 3-20 Examples Example for CS1W-INT01/CJ1W-INT01 When CIO 000000 turns ON in the following example, MSKR(692) reads the current mask status of Interrupt Input Unit 2 and stores it in D00100. 000000 MSKR D00100 D00100 0: Interrupt enabled 1: Interrupt masked When CIO 000001 turns ON in the following example, MSKS(690) reads the rising/falling edge designations for Interrupt Input Unit 0 and stores it in...
Page 777 Interrupt Control Instructions Section 3-20 Variations Variations Executed Each Cycle for ON Condition CLI(691) Executed Once for Upward Differentiation @CLI(691) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 778 Interrupt Control Instructions Section 3-20 The relationship between Interrupt Input Unit unit numbers and interrupt task numbers is shown in the following table. Unit Interrupt task numbers number 100 to 107 Bits 00 to 07 of S correspond to the input interrupt tasks.
Page 779 Interrupt Control Instructions Section 3-20 Area Auxiliary Bit Area A000 to A959 Timer Area T0000 to T4095 Counter Area C0000 to C4095 DM Area D00000 to D32767 EM Area without bank E00000 to E32767 EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767...
Page 780 Interrupt Control Instructions Section 3-20 2. Unit numbers are assigned to Interrupt Input Units in the order that they are mounted, from left to right. N = 4 or 5 Values 4 and 5 correspond to scheduled interrupts 2 and 3. When N is 4 or 5, the content of S specifies the time interval to the first sched- uled interrupt task after MSKS(690) is executed.
Page 781 Interrupt Control Instructions Section 3-20 000000 D00100 D00100 0: Recorded interrupt input retained 1: Recorded interrupt input cleared Example for C200HS-INT01 When CIO 000000 turns ON in the following example, CLI(691) clears the recorded interrupts for interrupt inputs 3 and 6 in Interrupt Input Unit 2. Example for Setting Time to First Scheduled Interrupt When CIO 000000 turns ON in the following example, CLI(691) sets the time to the first execution of scheduled interrupt 2 to 50 seconds.
Page 782 Interrupt Control Instructions Section 3-20 CS1-H, CJ1-H, and CJ1M CPU Units and Power OFF Interrupts When a CS1-H, CJ1-H, and CJ1M CPU Unit is being used, power OFF inter- rupt processing can be disabled simultaneously when A503 (the Disable Set- ting for Power OFF Interrupts) is set to A5A5 Hex.
Page 783 Interrupt Control Instructions Section 3-20 reset after execution of EI(694) in the event that a power interruption is detected during execution of the instructions between DI(693) and EI(694). Task No. 0 The mask on power OFF interrupt processing is enabled. Task No.
Page 784 Interrupt Control Instructions Section 3-20 Description EI(694) is executed from the main program to temporarily enable all interrupt tasks that were disabled by DI(693). DI(693) disables all interrupts except the power OFF interrupt (I/O interrupts, scheduled interrupts, and external inter- rupts).
Page 785 Interrupt Control Instructions Section 3-20 Disables execution of all interrupt tasks (except the power OFF interrupt). 000000 Enables execution of all disabled interrupt tasks. Note When the power OFF interrupt task is disabled for a CS1-H, CJ1-H, or CJ1M CPU Unit, power OFF processing will also be enabled at the same time. Task No.
Page 786 Interrupt Control Instructions Section 3-20 Operation of MSKS(690) Both I/O interrupt tasks and scheduled interrupt tasks are masked (disabled) when the PLC is first turned on. MSKS(690) can be used to unmask or mask I/O interrupts and set the time intervals for scheduled interrupts. In this example, MSKS(690) uses the contents of D00100 to unmask interrupt inputs 0 to 3 and mask interrupt inputs 4 to 7 from Interrupt Input Unit 0.
Page 787 Interrupt Control Instructions Section 3-20 After completion of interrupt task 3, recorded interrupts are executed in order of their priority. Since an input from interrupt input 0 was recorded, I/O inter- rupt task 0 (interrupt task 100) will be executed when task 3 is completed. Interrupt input 1 isn’t retained by CLI(691), so that input is cleared.
Page 788 Interrupt Control Instructions Section 3-20 3. The scheduled time interval setting and interrupt processing • Set the scheduled time interval with MSKS(690). • After MSKS(690) has been executed and the time to the first sched- uled interrupt (set with CLI(691)) has passed, the task currently being processed will be interrupted and the scheduled interrupt task will be executed.
Page 789 Interrupt Control Instructions Section 3-20 5. After scheduled interrupt processing has begun, the scheduled time inter- val can be changed by executing MSKS(690). In this case, the time interval is changed from 100 ms to 200 ms. 6. Scheduled interrupt processing is disabled by executing MSKS(690) with a time interval of 0000.
Page 790: High-Speed Counter/Pulse Output Instructions
High-speed Counter/Pulse Output Instructions Section 3-21 3-21 High-speed Counter/Pulse Output Instructions This section describes instructions used to control the high-speed counters and pulse outputs. Instruction Mnemonic Function Page code MODE CONTROL HIGH-SPEED COUNTER PV READ REGISTER COMPARISON TABLE CTBL SPEED OUTPUT SPED SET PULSES PULS...
Page 791: Cio 0000 To Cio 6142
High-speed Counter/Pulse Output Instructions Section 3-21 Port 0100 hex Interrupt input 0 in counter mode 0101 hex Interrupt input 1 in counter mode 0102 hex Interrupt input 2 in counter mode 0103 hex Interrupt input 3 in counter mode 1000 hex PWM(891) output 0 1001 hex PWM(891) output 1...
Page 792 Section 3-21 High-speed Counter/Pulse Output Instructions Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to – 2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description INI(880) performs the operation specified in C for the port specified in P.
Page 793 Section 3-21 High-speed Counter/Pulse Output Instructions Changing a PV (C = 0002 hex) If C is 0002 hex, INI(880) changes a PV as shown in the following table. Port and mode Operation Setting range Pulse output (P = 0000 or 0001 The present value of the 8000 0000 to 7FFF hex)
Page 794 High-speed Counter/Pulse Output Instructions Section 3-21 Example When CIO 000000 turns ON in the following example, SPED(885) starts out- putting pulses from pulse output 0 in Continuous Mode at 500 Hz. When CIO 000001 turns ON, pulse output is stopped by INI(880). 000000 @SPED D00100...
Page 795 Section 3-21 High-speed Counter/Pulse Output Instructions Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands P: Port Specifier P specifies the port to which the operation applies. Port 0000 hex Pulse output 0 0001 hex Pulse output 1 0010 hex High-speed counter 0 0011 hex...
Page 796 High-speed Counter/Pulse Output Instructions Section 3-21 Area Indirect DM/EM @ D00000 to @ D32767 addresses in binary Indirect DM/EM *D00000 to *D32767 addresses in BCD Constants See descrip- See descrip- tion of oper- tion of oper- and. and. Data Registers Index Registers Indirect addressing ,IR0 to ,IR15...
Page 797 High-speed Counter/Pulse Output Instructions Section 3-21 Reading Status (C = 0001 hex) If C is 0001 hex, PRV(881) reads status as shown in the following table. Port and Operation Results of reading mode Pulse out- The pulse output sta- D 0 0 0 0 0 0 0 0 tus is Pulse Output Status Flag stored in...
Page 798 Section 3-21 High-speed Counter/Pulse Output Instructions Flags Name Label Operation Error Flag ON if the specified range for P or C is exceeded. ON if the combination of P and C is not allowed. ON if reading range comparison results is specified even though range comparison is not being executed.
Page 799 High-speed Counter/Pulse Output Instructions Section 3-21 Variations Variations Executed Each Cycle for ON Condition CTBL(882) Executed Once for Upward Differentiation @CTBL(882) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 800: W000 To W511
High-speed Counter/Pulse Output Instructions Section 3-21 Lower word of range 1 lower limit 0000 0000 to FFFF FFFF hex (See note.) Upper word of range 1 lower limit TB+1 Lower word of range 1 upper limit TB+2 0000 0000 to FFFF FFFF hex (See note.) Upper word of range 1 upper limit TB+3 Range 1 interrupt task number...
Page 801 High-speed Counter/Pulse Output Instructions Section 3-21 cient to use the differentiated version (@CTBL(882)) of the instruction or an execution condition that is turned ON only for one scan. Note If an interrupt task that has not been registered is specified, a fatal program error will occur the first time an interrupt is generated.
Page 802 High-speed Counter/Pulse Output Instructions Section 3-21 • If there is no reason to execute an interrupt task, specify AAAA hex as the interrupt task number. The range comparison results can be read with PRV(881) or using the Range Comparison In-progress Flags. Note An error will occur if the upper limit is less than the lower limit for any one range.
Page 803 High-speed Counter/Pulse Output Instructions Section 3-21 Ladder Symbol SPED(885) P: Port specifier M: Output mode F: First pulse frequency word Variations Variations Executed Each Cycle for ON Condition SPED(885) Executed Once for Upward Differentiation @SPED(885) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas...
Page 804 High-speed Counter/Pulse Output Instructions Section 3-21 Area DM Area D00000 to D32766 EM Area without bank EM Area with bank Indirect DM/EM @ D00000 to @ D32767 addresses in binary Indirect DM/EM *D00000 to *D32767 addresses in BCD Constants See descrip- See descrip- See description of oper- tion of oper-...
Page 805 High-speed Counter/Pulse Output Instructions Section 3-21 Note Pulse output will stop immediately if the CPU Unit is changed to PROGRAM mode. Operation Purpose Application Frequency changes Description Procedure/ instruction Starting To output Changing the Outputs pulses at a SPED(885) (Con- Pulse frequency pulse output with spec-...
Page 806 High-speed Counter/Pulse Output Instructions Section 3-21 4. The direction set in the SPED(885) operand will be ignored if the number of pulses is set with PULS(881) as an absolute value. Operation Purpose Application Frequency changes Description Procedure/ instruction Starting To output Positioning Starts outputting PULS(886)
Page 807 High-speed Counter/Pulse Output Instructions Section 3-21 Flags Name Label Operation Error Flag ON if the specified range for P, M, or F is exceeded. ON if PLS2(887) or ORG(889) is already being executed to control pulse output for the specified port. ON if SPED(885) or INI(880) is used to change the mode between continuous and independent output during pulse output.
Page 808 High-speed Counter/Pulse Output Instructions Section 3-21 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands P: Port Specifier The port specifier indicates the port. The parameters set in D and N will apply to the next SPED(885) or ACC(888) instruction in which the same port output location is specified.
Page 809 High-speed Counter/Pulse Output Instructions Section 3-21 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description PULS(886) sets the pulse type and number of pulses specified in T and N for the port specified in P.
Page 810 High-speed Counter/Pulse Output Instructions Section 3-21 3-21-6 PULSE OUTPUT: PLS2(887) (CJ1M-CPU22/CPU23 Only) Purpose PLS2(887) outputs a specified number of pulses to the specified port. Pulse output starts at a specified startup frequency, accelerates to the target fre- quency at a specified acceleration rate, decelerates at the specified decelera- tion rate, and stops at approximately the same frequency as the startup frequency.
Page 811 High-speed Counter/Pulse Output Instructions Section 3-21 S: First Word of Settings Table The contents of S to S+5 control the pulse output as shown in the following diagrams. 1 to 2,000 Hz (0001 to 07D0 hex) Acceleration rate 1 to 2,000 Hz (0001 to 07D0 hex) Deceleration rate S1+1 Specify the increase or decrease in the frequency per pulse control period (4 ms).
Page 812 High-speed Counter/Pulse Output Instructions Section 3-21 Area Index Registers Indirect addressing ,IR0 to ,IR15 ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,IR0+(++) to ,IR15+(++)
Page 813 High-speed Counter/Pulse Output Instructions Section 3-21 Independent Mode Positioning Note Pulse output will stop immediately if the CPU Unit is changed to PROGRAM mode. Opera- Purpose Application Frequency changes Description Procedure/ tion instruction Start- Complex Positioning with Accelerates and decel- PLS2(887) Pulse frequency Specified number...
Page 814 High-speed Counter/Pulse Output Instructions Section 3-21 Opera- Purpose Application Frequency changes Description Procedure/ tion instruction Chang- Changing the tar- PLS2(887) can be exe- PULS(886) Number of pulses ↓ ing set- change get position and cuted during position- Number of changed with Pulse tings, target...
Page 815 High-speed Counter/Pulse Output Instructions Section 3-21 Note Triangular Control If the specified number of pulses is less than the number required to reach the target frequency and return to zero, the function will automatically reduce the acceleration/deceleration time and perform triangular control (acceleration and deceleration only.) An error will not occur.
Page 816 High-speed Counter/Pulse Output Instructions Section 3-21 Flags Name Label Operation Error Flag ON if the specified range for P, M, S, or F is exceeded. ON if PLS2(887) is executed for a port that is already out- putting pulses for SPED(885) or ORG(889). ON if PLS2(887) is executed in an interrupt task when an instruction controlling pulse output is being executed in a cyclic task.
Page 817 High-speed Counter/Pulse Output Instructions Section 3-21 Variations Variations Executed Each Cycle for ON Condition ACC(888) Executed Once for Upward Differentiation @ACC(888) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands...
Page 818 High-speed Counter/Pulse Output Instructions Section 3-21 Area Indirect DM/EM @ D00000 to @ addresses in binary D32767 Indirect DM/EM *D00000 to *D32767 addresses in BCD Constants See description See description of operand. of operand. Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to...
Page 819 High-speed Counter/Pulse Output Instructions Section 3-21 Continuous Mode Speed Control Pulse output will continue until it is stopped from the program. Note Pulse output will stop immediately if the CPU Unit is changed to PROGRAM mode. Operation Purpose Application Frequency changes Description Procedure/ instruction...
Page 820 High-speed Counter/Pulse Output Instructions Section 3-21 Operation Purpose Application Frequency changes Description Procedure/ instruction Stopping To stop Immediate stop Immediately stops ACC(888) Pulse frequency pulse output pulse out- pulse output. (Continu- ous) Present frequency ↓ INI(880) (Continu- ous) Time Execution of ACC(888) Execution of INI880) To stop Immediate stop Immediately stops...
Page 821 High-speed Counter/Pulse Output Instructions Section 3-21 4. The direction set in the ACC(888) operand will be ignored if the number of pulses is set with PULS(881) as an absolute value. Opera- Purpose Application Frequency changes Description Procedure/ tion instruction Starting Simple trap- Positioning with Accelerates and...
Page 822 High-speed Counter/Pulse Output Instructions Section 3-21 target frequency and return to zero, the function will automatically reduce the acceleration/deceleration time and perform triangular control (acceleration and deceleration only.) An error will not occur. Specified number of pulses Pulse frequency (Specified with PLS2(887).) Target frequency...
Page 823 High-speed Counter/Pulse Output Instructions Section 3-21 3-21-8 ORIGIN SEARCH: ORG(889) (CJ1M-CPU22/CPU23 Only) Purpose ORG(889) performs an origin search or origin return operation. This instruction is supported by the CJ1M-CPU22/CPU23 CPU Units only. Origin Search Pulses are output using the specified method to actually drive the motor and establish the origin based on origin proximity input and origin input signals.
Page 824 High-speed Counter/Pulse Output Instructions Section 3-21 Area Timer Area Counter Area DM Area EM Area without bank EM Area with bank Indirect DM/EM addresses in binary Indirect DM/EM addresses in BCD Constants See description of operand. See description of operand. Data Registers Index Registers Indirect addressing...
Page 825 High-speed Counter/Pulse Output Instructions Section 3-21 the operating mode, origin detection method, and other parameters. Refer to the CJ-series Built-in I/O Operation Manual for details. Origin Proximity Input Signal Origin Input Signal Pulse frequency Origin search high speed Origin search Origin search deceleration rate acceleration rate...
Page 826 High-speed Counter/Pulse Output Instructions Section 3-21 Example When CIO 000000 turns ON in the following programming example, ORG(889) starts an origin return operation for pulse output 0 by outputting pulses using the CW/CCW method. According to the PLC Setup, the initial speed is 100 pps, the target speed is 200 pps, and the acceleration and deceleration rates are 50 Hz/4 ms.
Page 827 High-speed Counter/Pulse Output Instructions Section 3-21 F: Frequency F specifies the frequency of the pulse output between 0.1 and 6,553.5 Hz (0.1 Hz units, 0001 to FFFF hex). The accuracy of the PMW(891) waveform that is actually output (ON duty +5%/ − 0%) applies only to 0.1 to 1,000.0 Hz due to limitations in the output circuits.
Page 828: Step Instructions
Step Instructions Section 3-22 Flags Name Label Operation Error Flag ON if the specified range for P, F, or D is exceeded. ON if pulses are being output using ORG(889) for the specified port. ON if PWM(891) is executed in an interrupt task when an instruction controlling pulse output is being executed in a cyclic task.
Page 829 Step Instructions Section 3-22 Corresponds Starts the step programming area a turns ON Proceeds to the next step Process A Process A repeated until b turns ON. Process A b turns ON Process B Process B repeated until c turns ON. Process B c turns ON Process C...
Page 830 Step Instructions Section 3-22 When defining the beginning of a step, a control bit is specified as follows:. STEP(008) B: Bit When defining the end of a step a control bit is not specified as follows: STEP(008) Variations Variations Executed Each Cycle for ON Condition STEP(008)/ SNXT(009) Executed Once for Upward Differentiation...
Page 831 Step Instructions Section 3-22 The step programming area is from the first STEP(008) instruction (which always takes a control bit) to the last STEP(008) instruction (which never takes a control bit). Starting Step Execution SNXT(009) is placed at the beginning of the step programming area to start step execution.
Page 832 Step Instructions Section 3-22 Interlock Status (IL) Instruction output Status Bits specified for OUT, OUT NOT All OFF The following timer instruc- 0000 hex (reset) tions: TIM, TIMX(551), Completion Flag OFF (reset) TIMH(015), TIMHX(551), TMHH(540), TIMHHX(552), TIML(542), and TIMLX(553) Bits or words specified for other instructions (see note) Holds the previous status (but the instructions are not executed)
Page 833 Step Instructions Section 3-22 A20012 (Step Flag) is turned ON for one cycle when STEP(008) is executed. This flag can be used to conduct initialization once the step execution has started. Placement Conditions for Step Programming Areas (STEP B to STEP) STEP(008) and SNXT(009) cannot be used inside of subroutines, interrupt programs, or block programs.
Page 834 Step Instructions Section 3-22 Step a starts when C turns ON A executed When d turns ON, b starts (A is interlocked) B executed e turns ON (B is interlocked) End of step programming area Normal ladder Returns to normal ladder program program...
Page 835 Step Instructions Section 3-22 CIO 00000 turns ON, step W00000 starts Step W00000 starts from the next instruction Step W00000 Step (A) ladder program W00000 turns OFF, W00001 turns ON and step W00001 starts Step W00001 starts from the next instruction Step (B) ladder program W00001 turns OFF and dummy bit W10000 turns ON End of step programming area...
Page 836 Step Instructions Section 3-22 Step W00000 (A) Step (A) ladder program Step W00001 (B) Step (B) ladder program Step W00002 (C) Step (C) ladder program Branching Control 000001 (Step (A) 000002 (Step (B) starting condition) starting condition) Step (B) W00001 Step (A) W00000 →...
Page 837 Step Instructions Section 3-22 ↑ ↑ Step W00000 Step (A) ladder program Step W00001 Step (B) ladder program Step W00002 Step (C) ladder program The above programming is used when steps A and B cannot be executed simultaneously. For simultaneous execution of A and B, delete the execution conditions illustrated below.
Page 838 Step Instructions Section 3-22 Parallel Control 000001 (Step (A), (C) simultaneous starting condition) Step (A) W00000 Step (C) W00002 000002 (Step (A) 000003 (Step (C) → Step (D) → Step (B) transi- transition condition) tion condition) Step (B) W00001 Step (D) W00002 000004 (When both Step (B) and Step (D) are complete, moves to Step (E) Step (E) W00004...
Page 839 Step Instructions Section 3-22 Step W00000 (A) Step (A) ladder program Step W00001 Step (B) ladder program Step W00002 (C) Step (C) ladder program Step W00003 Step (D) ladder program Step (E) ladder program Step W00004...
Page 840 Step Instructions Section 3-22 Application Examples The following three examples demonstrate the three types of execution con- trol possible with step programming. Example 1 demonstrates sequential exe- cution; Example 2, branching execution; and Example 3, parallel execution. Example 1: The following process requires that three processes, loading, part installation, Sequential Execution and inspection/discharge, be executed in sequence with each process being reset before continuing on the next process.
Page 841 Step Instructions Section 3-22 Address Instruction Operands Process 000000 000001 A started. 000001 SNXT(009) W00000 000002 STEP(008) W00000 Process A 000100 000002 Programming for process A 000101 SNXT(009) W00001 000102 STEP(008) W00001 Process A reset. Process B Process B started. 000100 000003 000101...
Page 842 Step Instructions Section 3-22 The following diagram demonstrates the flow of processing and the switches that are used for execution control. Here, either process A or process B is used depending on the status of SW A1 and SW B1. SW B1 SW A1 Process A...
Page 843 Step Instructions Section 3-22 The program for this process, shown below, starts with two SNXT(009) instructions that start processes A and B. Because of the way CIO 000001 (SW A1) and CIO 000002 (SW B1) are programmed, only one of these will be executed with an ON execution condition to start either process A or process B.
Page 844 Step Instructions Section 3-22 Example 3: The following process requires that two parts of a product pass simulta- neously through two processes each before they are joined together in a fifth Parallel Execution process. Various sensors are positioned to signal when processes are to start and end.
Page 845 Step Instructions Section 3-22 Address Instruction Operands Process A started. 000000 @LD 000001 Process C 000001 SNXT(009) W00000 started. 000002 SNXT(009) W00002 000003 STEP(008) W00000 Process A 000100 000002 000101 SNXT(009) W00001 Programming for process A 000102 STEP(008) W00001 Process A Process B reset.
Page 846: Basic I/O Unit Instructions
Basic I/O Unit Instructions Section 3-23 3-23 Basic I/O Unit Instructions This section describes instructions used with I/O Units. Instruction Mnemonic Function code Page I/O REFRESH IORF 7-SEGMENT DECODER SDEC INTELLIGENT I/O READ IORD INTELLIGENT I/O WRITE IOWR 3-23-1 I/O REFRESH: IORF(097) Purpose Refreshes the specified I/O words.
Page 847 Basic I/O Unit Instructions Section 3-23 Area Data Registers Index Registers Indirect addressing using ,IR0 to 15 Index Registers –2048 to +2047, IR0 to 15 DR0 to 15, IR0 to 15, IR0 to 15+(++) ,–(– –) IR0 to 15 Description IORF(097) refreshes the I/O words between St and E, inclusively.
Page 848 Basic I/O Unit Instructions Section 3-23 Flags Name Label Operation Error Flag ON if St is greater than E. ON if the address is out of range for an indirect IR specifi- cation for St. ON if the address is out of range for an indirect IR specifi- cation for E.
Page 849: E00000 To E32767
Basic I/O Unit Instructions Section 3-23 3-23-2 7-SEGMENT DECODER: SDEC(078) Purpose Converts the hexadecimal contents of the designated digit(s) into 8-bit, 7-seg- ment display code and places it into the upper or lower 8-bits of the specified destination words. Ladder Symbol SDEC(078) S: Source word Di: Digit designator...
Page 850: E00000 To @ 32767
Basic I/O Unit Instructions Section 3-23 Area Indirect DM/EM @D00000 to @D32767 addresses in binary @E00000 to @E32767 @En_00000 to @En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Specified values...
Page 851 Basic I/O Unit Instructions Section 3-23 Di: 0100 S: D00100 Hexadecimal to 7-segment data conversion 71, 1 06, and 2 7-segment Data The following table shows the data conversions from a hexadecimal digit (4 bits) to 7-segment code (8 bits). Original data Converted code (segments) Display...
Page 852: En_00000 To
Basic I/O Unit Instructions Section 3-23 3-23-3 INTELLIGENT I/O READ: IORD(222) Purpose Reads the contents of the I/O Unit’s memory area. Ladder Symbol IORD(222) C: Control data S: Transfer source and number of words D: Transfer destination Variations Variations Executed Each Cycle for ON Condition IORD(222) Executed Once for Upward Differentiation @IORD(222)
Page 853: Dr0 To Dr15
Basic I/O Unit Instructions Section 3-23 Area Constants #0000 to #FFFF Specified values only (binary) Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 854 Basic I/O Unit Instructions Section 3-23 • The designated Special I/O Unit is on SYSMAC BUS. • A Special I/O Unit not affected by IORD(222) is designated. • A Special I/O Unit with a Special I/O Unit setting error or a Special I/O Unit error is designated.
Page 855 Basic I/O Unit Instructions Section 3-23 Example In this example, IORD(222) is used to read data. When CIO 000000 is turned ON, 10 words are read from the Special I/O Unit with unit number 3, and are stored in D00100 to D00109. Number of words Unit number: 3 to transfer: 10...
Page 856 Basic I/O Unit Instructions Section 3-23 Operand Specifications Area CIO Area CIO 0000 to CIO 6143 CIO 0000 to CIO 6142 Work Area W000 to W511 W000 to W510 Holding Bit Area H000 to H511 H000 to H510 Auxiliary Bit Area A000 to A959 A000 to A958 Timer Area...
Page 857 Basic I/O Unit Instructions Section 3-23 Flags Name Label Operation Error Flag ON if the number of words to transfer (D) is outside the range of 0001 to 0080 hex. ON if the unit number (D) is outside the range of 0000 to 005F hex.
Page 858 Basic I/O Unit Instructions Section 3-23 IOWR When the input condition is met, self maintenance is performed by output A and IOWR(223) is executed with each cycle until the Equals Flag turns ON. When the writing is completed and the Equals Flag turns ON, output B turns ON and the self maintenance is cleared.
Page 859 Basic I/O Unit Instructions Section 3-23 Ladder Symbol DLNK(226) N: Unit number Variations Variations Executed Each Cycle for ON Condition DLNK(226) Executed Once for Upward Differentiation @DLNK(226) Executed Once for Downward Differentiation Not supported Immediate Refreshing Specification Not supported Applicable Program Areas Block program areas Step program areas Subroutines...
Page 860 Basic I/O Unit Instructions Section 3-23 2. Data specific the CPU Bus Unit such as data link data or DeviceNet Re- mote I/O Communications data (refreshed together with the data in the CPU Bush Unit Areas) CPU Bus Unit Data refreshing specific to the Unit Controller Link Unit or SYSMAC Data link refreshing Link Unit...
Page 861 Basic I/O Unit Instructions Section 3-23 Flags Name Label Operation Error Flag ON if the specified unit number is not between 0000 and 000F Hex (between 0 and 15 decimal). ON if the PLC does not have a CPU Bus Unit with the specified unit number.
Page 862 Basic I/O Unit Instructions Section 3-23 W000 000000 DLNK &1 Equals Flag W001 W001 Equals Flag W000 Controller Link Unit with unit number 1 000000 DLNK Refresh &1 Data link refreshing Data link area Controller Link The actual timing for data link area refreshing in this example is as follows: •...
Page 863: Serial Communications Instructions
Serial Communications Instructions Section 3-24 • Transferring Data with Execution of DLNK(226) Cycle time Refreshing data link data within PLC Data transfer processing Data link One communications cycle time 3-24 Serial Communications Instructions This section describes instructions used for serial communications. Instruction Mnemonic Function code...
Page 864 Serial Communications Instructions Section 3-24 serial ports on the Serial Communications Board (CS Series only) or Serial Communications Unit. Instructions Communications frames Function TXD(236) Sends or receives data in one direction only. Any of the following can be used. A send delay can be set. No Start or End Code Start and End Code RXD(235)
Page 865 Serial Communications Instructions Section 3-24 3-24-2 PROTOCOL MACRO: PMCR(260) Purpose Calls and executes a communications sequence registered in a Serial Com- munications Board (CS Series only) or Serial Communications Unit. Ladder Symbol PMCR(260) C1: Control word 1 C2: Control word 2 S: First send word R: First receive word Variations...
Page 866 Serial Communications Instructions Section 3-24 If there is no send data, always set 0000 as a constant for S. An error will occur and the Error Flag will turn ON if any other constant or a word address is given and PMCR(260) will not be executed. Number of send words + 1 n words of data must be prepared in advance.
Page 867 Serial Communications Instructions Section 3-24 Area Constants Specified 0000 to #0000 (binary) values only 03E7Hex (0 to 999) Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(–...
Page 868 Serial Communications Instructions Section 3-24 Refer to the CX-Protocol Operation Manual (W344) for procedures for desig- nating symbols R( ) and W( ). PMCR(260) can be executed for a serial communications port on a Serial Communications Board (CS Series only) or Serial Communications Unit. Up to 16 Serial Communications Units can be mounted to the CPU Rack and Expansion I/O Racks.
Page 869 Serial Communications Instructions Section 3-24 CPU Unit PMCR(260) PMCR(260) The Error Flag will turn ON in the following cases. • The corresponding Communications Port Enable Flag is OFF for the specified logical port (0 to 7) when PMCR(260) is executed. •...
Page 870 Serial Communications Instructions Section 3-24 Name Address Contents Communications Port Error A21900 to ON when an error occurs in network Flag A21907 communications. Bits 00 to 07 correspond to logical ports 0 to 7, respectively. Flag status will be maintained until the next network communications start.
Page 871 Serial Communications Instructions Section 3-24 Inner Board Area (CS Series Only) Name Address Contents Port 1 Protocol Macro Exe- CIO 190915 ON when PMCR(260) is executed. The cution Flag flag will remain OFF if execution fails. The flag will turn OFF when the com- Port 2 Protocol Macro Exe- CIO 191915 munications sequence has been com-...
Page 872 Serial Communications Instructions Section 3-24 Protocol Communica- Macro tions Port En- Execution abled Flag Flag Unit address of communications partner E1 hex: Inner Board Serial port number (physical port) 2 hex: Port 2 Communications port number (logical port) 7 hex: Logical port 7 Communications sequence number 0065 hex: 101 Sent...
Page 873 Serial Communications Instructions Section 3-24 The following programming example shows the instructions used to con- stantly or periodically execute PMCR(260) to read data through a single receive operation. Protocol Communica- Macro tions Port En- Execution Always ON abled Flag Flag Flag Receive buffer...
Page 874 Serial Communications Instructions Section 3-24 3-24-3 TRANSMIT: TXD(236) Purpose Outputs the specified number of bytes of data from the RS-232C port built into the CPU Unit. Ladder Symbol TXD(236) S: First source word C: Control word N: Number of bytes 0000 to 0100 hex (0 to 256) Variations Variations...
Page 875 Serial Communications Instructions Section 3-24 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants Specified values #0000 to #0100 only (binary) Data Registers DR0 to DR15 Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers...
Page 876 Serial Communications Instructions Section 3-24 Flags Name Label Operation Error Flag ON if the no-protocol mode is not set in the PLC Setup. ON if the value of C is not within range. ON if the value for N is not between 0000 and 0100 hex. ON if a send is attempted when the Send Ready Flag is OFF.
Page 877 Serial Communications Instructions Section 3-24 Related Flags and Words The following PLC Setup settings and Auxiliary Area flag can be used as required when executing TXD(236). PLC Setup Name Contents Setting No-protocol Mode Specifies if a start code is to be used in the 0: None Start Code frame format for no-protocol mode communi-...
Page 878 Serial Communications Instructions Section 3-24 Example: Sending Data When CIO 000000 is ON in the following example, 10 bytes of data starting in D00100 are sent as shown without any conversion. &10 C: D00200 Byte order 1: Least significant bytes first RS and ER signal control Not used.
Page 879 Serial Communications Instructions Section 3-24 Example: Performing When CIO 000001 is ON in the following example, the RS signal and ER sig- nal are set according to the respective statuses of bits 15 and 14 in D00300. Signal Control C: D00400 Byte order 0: Disabled RS and ER signal control...
Page 880 Serial Communications Instructions Section 3-24 Operands The contents of the control word, C, is as shown below. Byte order 0: Most significant bytes first 1: Least significant bytes first CS and DR signal monitoring Not used. 0: No CS and DR signal monitoring 1: CS signal monitoring 2: DR signal monitoring 3: CS and DR signal monitoring.
Page 881 Serial Communications Instructions Section 3-24 No Start or End Code 1 2 3 4 5 6 0... Receive bytes: Specified in the PC Setup Only Start Code 1 2 3 4 5 6 0... Receive bytes after ST: Specified in the PC Setup Only End Code 1 2 3 4 5 6 0...
Page 882 Serial Communications Instructions Section 3-24 • Start code: None or 00 to FF hex • End code: None, CR+LF, or 00 to FF hex. If no end code is specified, the number of bytes to received is set from 00 to FF hex (1 to 256 decimal; 00 is used to specify 256 bytes).
Page 883 Serial Communications Instructions Section 3-24 Related Flags and Words The following PLC Setup settings and Auxiliary Area flag can be used as required when executing RXD(235). PLC Setup Name Contents Setting No-protocol Mode Start Specifies if a start code is to be used in the 0: None Code frame format for no-protocol mode commu-...
Page 884 Serial Communications Instructions Section 3-24 Examples When CIO 000000 is ON in the following example, data is received from the RS-232C port and 10 bytes of data are stored starting in D00100. &10 C: D00200 Byte order 1: Least significant bytes first CS and DR signal monitoring 0: No CS and DR signal monitoring Not used.
Page 885 Serial Communications Instructions Section 3-24 Operands The contents of the control word, C, are as shown below. Unit address of port device CPU Unit: 00 hex CPU Bus Unit: Unit number + 10 hex Inner Board: E1 hex (CS Series only) Serial port number 1 hex: Peripheral port on CPU Unit or Port 1 on CPU Bus Unit or Inner Board 2 hex: Built-in RS-232C port on CPU Unit or Port 2 on CPU Bus Unit or Inner Board...
Page 886 Serial Communications Instructions Section 3-24 ing table. When the constant #0000 is designated to S, the communications settings of the corresponding port will be set to default. Unit address Unit Port No. Serial port Serial port communications setup area 00 Hex CPU Unit 1 hex Port 1...
Page 887 Serial Communications Instructions Section 3-24 Related Flags and Words The following flags can be used as required when executing STUP(237). These flags are in the Auxiliary Area. Name Address Contents Peripheral Port Parameters A61901 ON when the communications param- Changing Flag eters are being changed for the periph- eral port.
Page 888: Network Instructions
Network Instructions Section 3-25 3-25 Network Instructions 3-25-1 About SYSMAC NET Link/SYSMAC LINK Operations The network instructions can be divided into two types, SEND(090)/ RECV(098) and CMND(490). These instructions are transmitted between Units (CPU Units, CPU Bus Units, and computers) in a network to transfer data and control operation, such as changing the operating mode.
Page 889 Network Instructions Section 3-25 d) Inner Board (CS Series only): E1 hexadecimal e) Computer: Unit number Destination device (hexadecimal) Node number Unit number +10 Node number Node number Node number Note It is also possible to specify a serial port (1 through 4) within the destination device.
Page 890 Network Instructions Section 3-25 PLC to computer Communications to a Serial Port in the Network These examples show communications from a PLC to serial ports in devices in the network. The first shows communications to serial ports in devices in another PLC (the CPU Unit, CPU Bus Unit, or Inner Board) and the second shows communications to a serial port within the CPU Rack itself.
Page 891 Network Instructions Section 3-25 Host computer connected to Host computer connected to a Host computer connected to a the CPU Unit's built-in port Serial Communications Board Serial Port Unit (CS Series only) Host computer Host computer Host computer To port To port To port CPU Unit...
Page 892 Network Instructions Section 3-25 Communications Flags The operation of the communications flags is outlined below. • The Communications Port Enabled Flag is reset to 0 when communica- tions are in progress and set to 1 when communications are completed (normally or not). •...
Page 893 Network Instructions Section 3-25 The following diagram shows an example of exclusive control. Bit A remains ON while the communications KEEP A instruction is being executed. Execution Communications condition Port Enabled Flag Reset B Copies the operand and control data to the Creates op- desired data area.
Page 894 Network Instructions Section 3-25 Example of Previous Programming Requirements Exclusive control was required by the user when the same communications port was used more than once. Confirmation of the availability of a communications port was required using the corresponding Communications Port Enabled Flag, here for port 0. Execution condition (Executing)
Page 895 Network Instructions Section 3-25 Auxiliary Area Bits and Words Used when Automatically Allocating Communications Ports Address Bits Name Description A202 Network Communications Port ON when there is a communications port available for automatic Allocation Enabled Flag allocation. This flag can be used to confirm if all eight communica- tions ports have already been allocated before executing communi- cations instructions.
Page 896 Network Instructions Section 3-25 2. The Auxiliary Area bits and words used for user-specified communications ports are listed in the following table. Address Bits Name Description A202 00 to 07 Communications Port Enabled ON when a communications instruction can be executed with the Flags corresponding port number.
Page 897 Network Instructions Section 3-25 Applications Methods To use automatic communications port allocation, set the communications port number of “F” and then program as shown below. Completing and Processing Error after Executing Communications Instructions Execution condition KEEP (Executing) d (Execution completed) When a (Executing) turns ON, a communications instruction a (Executing) (SEND(090), RECV(098), CMND(490), or PMCR(260)) is executed with the...
Page 898 Network Instructions Section 3-25 Accessing the Completion Code after Executing Communications Instructions The completion codes are generally used to troubleshoot errors when they occur. A completion code of 0000 hex can, however, also be used to confirm that communications have completed normally. Execution condition KEEP (Executing)
Page 899 Network Instructions Section 3-25 Programming Example W00000 A20201 Port: 1 Communications were previously enabled by exclusively controlling operation using W00000 W00001 A20201 and W00001. Automatic port alloca- Port: 1 tion was add- ed to the pro- gram. This instruction may, at times, use communications port 1.
Page 900 Network Instructions Section 3-25 Note When SEND(090) is being executed, the contents of S and D are read and a FINS command for data transmission is composed. When RECV(098) is being executed, the content of S is read and a FINS command for data reception is composed.
Page 901 Network Instructions Section 3-25 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands C: First control word The five control words C to C+4 specify the number of words being transmit- ted, the destination, and other settings shown in the following table. Word Bits 00 to 07 Bits 08 to 15...
Page 902 Network Instructions Section 3-25 4. The unit address indicates the Unit, as shown in the following table. Unit Unit address setting CPU Unit 00 hex CPU Bus Unit 10 hex + unit number Special I/O Unit (except 20 hex + unit number C200H-series Special I/O Units) Inner Board (CS Series...
Page 903 Network Instructions Section 3-25 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047, IR0 to –2048 to +2047, IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description SEND(090) transfers the data beginning at word S to addresses beginning at D in the designated device through the PLC’s CPU Bus or over a network.
Page 904 Network Instructions Section 3-25 Transmission through When the CPU Unit’s built-in serial port, a Serial Communications Board (CS- series only), or Serial Communications Unit is in host link mode and con- Host Link nected one-to-one with a host computer, SEND(090) can be executed to transmit data from the PLC to the host computer the next time that the PLC has the right to transmit.
Page 905 Network Instructions Section 3-25 The following table shows relevant bits and flags in the Auxiliary Area. Name Address Operation Communications A20200 to These flags are turned ON to indicate that net- Port Enabled Flag A20207 work instructions, including PMCR(260) may be executed for the corresponding ports (00 to 07).
Page 906 Network Instructions Section 3-25 Input condition A20200 @SEND 0100 C D00200 0 0 0 A Number of words to send: 10 words 0000 C+1 D00201 0 1 0 0 Transmit to network 0 and port 1 of Serial Communications Board D00200 C+2 D00202 0 0 1 0 Node number 0, unit address 10...
Page 907 Network Instructions Section 3-25 Operands C: First control word The five control words C to C+4 specify the number of words to be received, the source of the transmission, and other settings shown in the following table. Word Bits 00 to 07 Bits 08 to 15 Number of words: 0001 to maximum allowed (4-digit hexadecimal)
Page 908 Network Instructions Section 3-25 6. Refer to Automatic Allocation of Communications Ports on page 872 for details on using automatic allocation of the communications port number (logical port). Operand Specifications Area CIO Area CIO 0000 to CIO 6143 CIO 0000 to CIO 6139 Work Area W000 to W511...
Page 909 Network Instructions Section 3-25 RECV(098) can be used to request a data transmission from a particular serial port in the source device as well as the device itself. Data can be received from a host computer connected to the PLC’s serial port (when set to host link mode) as well as a PLC or computer connected through a Controller Link or Ethernet network.
Page 910 Network Instructions Section 3-25 Flags Name Label Operation Error Flag ON if the serial port number specified in C+1 is not within the range of 00 to 04. ON if the Communications Port Enabled Flag is OFF for the communications port number specified in C+3. OFF in all other cases.
Page 911 Network Instructions Section 3-25 3-25-4 DELIVER COMMAND: CMND(490) Purpose Sends an FINS command and receives the response. Refer to the CS/CJ Series Communications Commands Reference Manual for details on FINS commands. Ladder Symbol CMND(490) S: First command word D: First response word C: First control word Variations Variations...
Page 912 Network Instructions Section 3-25 and the remainder of the words set aside for the response will be left un- changed. 3. Set the destination network address to 00 to transmit within the local net- work. When two or more CPU Bus Units are mounted, the network address will be the unit number of the Unit with the lowest unit number.
Page 913 Network Instructions Section 3-25 Area EM Area without bank E00000 to E32767 E00000 to E32762 EM Area with bank En_00000 to En_32767 En_00000 to En_32763 (n = 0 to C) (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767...
Page 914 Network Instructions Section 3-25 • Response monitoring time: (bits 00 to 15 of C+5): 0000 to FFFF Hex (but 0000 will specify 6553.5 s, and not 2 s as normal) If the destination node number is set to FF, the command data will be broad- cast to all of the nodes in the designated network.
Page 915 Network Instructions Section 3-25 enclosed between a host link header and terminator. Any FINS command command can be sent; the host link header code is 0F hexadecimal. A program must be created in the host computer to process the received com- mand (the FINS command enclosed in the host link header and terminator).
Page 916 Network Instructions Section 3-25 Name Address Operation Communications A203 to These words contain the completion codes for the Port Completion A210 corresponding ports (00 to 07) following execu- Codes tion of a network instruction. The corresponding word will contain 0000 while the network instruction is being executed and the completion code will be written when the instruc- tion is completed.
Page 917 TORY) to the local CPU Unit. The response is stored in D00100 to D00101. Here, the FINS command will create a directory called CS/CJ under the OMRON directory. The command code (2 bytes) and the end code (2 bytes) will be returned and stored as the response.
Page 918: File Memory Instructions
0 0 0 6 Directory name length: 0006 (6 characters) S+10: D00016 5 C 4 F S+11: D00017 4 D 5 2 Absolute directory path: \OMRON S+12: D00018 4 F 4 E 15 8 7 D00000 0 0 1 A...
Page 919 File Memory Instructions Section 3-26 will not be able to use the Memory Card even if it is reformatted in the CPU Unit. Number of Files in Root Directory There is a limit to the number of files that can be placed in the root directory of a Memory Card (just as there is a limit for a hard disk).
Page 920 File Memory Instructions Section 3-26 Execution A34315 A34313 condition FREAD File Memory Memory Card Operation Recognized Flag Flag 3-26-2 READ DATA FILE: FREAD(700) Purpose Reads the specified data or amount of data from the specified data file in file memory to the specified data area in the CPU Unit. Ladder Symbol FREAD(700) C: Control word...
Page 921 File Memory Instructions Section 3-26 File memory specifier 0: Memory Card 1: EM file memory Function specifier 0: Read data. 1: Read number of words. Carriage returns 0: No returns 8: Return every 10 fields* 9: Return every 1 field* A: Return every 2 fields* B: Return every 4 fields* C: Return every 5 fields*...
Page 922 File Memory Instructions Section 3-26 S1+2 and S1+3: First Source Word The 8-digit hexadecimal value in S1+2 and S1+3 specifies the starting read word from the beginning of the file. S1+3 S1+2 S1+3 contains the leftmost 4 digits and S1+2 contains the rightmost 4 digits. Data type Bits 12 to 15 of C Contents of S1+2 and S1+3...
Page 923 File Memory Instructions Section 3-26 "\" "A" "B" "C" → S2+1 S2+1 "\" "X" S2+2 S2+2 "Y" "Z" S2+3 S2+3 S2+4 S2+4 D: First Destination Word When data is being read, D specifies the starting address where the data read from file memory will be stored.
Page 924 File Memory Instructions Section 3-26 Operand Specifications Area CIO Area CIO 0000 to CIO 0000 to CIO 0000 to CIO 6143 CIO6143 CIO 6140 Work Area W000 to W000 to W000 to W511 W511 W508 Holding Bit Area H000 to H511 H000 to 508 H000 to W511 Auxiliary Bit Area A000 to A959...
Page 925 File Memory Instructions Section 3-26 The following table shows relevant flags in the Auxiliary Area. Name Address Operation Memory Card Type A34300 to Contains a binary number indicating the type A34302 of Memory Card, if any, that is installed. (0: None, 4: Flash ROM) Memory Card Format A34307 ON when the Memory Card is not formatted or...
Page 926 File Memory Instructions Section 3-26 The time required to complete data transfer for FREAD(700) will depend on the amount of data being transferred, the service time allocated to file access processing, and other conditions. As a guideline, the transfer times for a cycle time of 10 ms for a file in the root directory with the default service time set- tings will be 0.92 s for 1,024 words and 4.64 s for 9,999 words.
Page 927 File Memory Instructions Section 3-26 3-26-3 WRITE DATA FILE: FWRIT(701) Purpose Overwrites or appends data in the specified data file in file memory with the specified data from the data area in the CPU Unit. If the specified file doesn’t exist, a new file is created with that filename.
Page 928 File Memory Instructions Section 3-26 2. With double-words, the first word of data is read from the higher memory address, e.g., 12345678 would be written with 1234 from D00001 and 5678 from D00000. 3. If delimiting is specified, the specified of delimiter is added after every word for word data types and after every two words for double-word data types.
Page 929 File Memory Instructions Section 3-26 writing data with carriage returns (i.e., bits 08 to 11 of C set to between 8 and D Hex). 2. D1 to D1+3 must be in the same data area. 3. If the specified starting word exceeds the number of words in the data file, the File Write Error Flag (A34308) will be turned ON and the data won’t be written.
Page 930 File Memory Instructions Section 3-26 The source data is read from absolute internal memory addresses in RAM, so the entire block of data will be read even if the data spans two or more data areas. For example, if the first destination address is in the Work Area but the amount of data exceeds the capacity of this area, FWRIT(701) will continue reading data at the beginning of the next area (in this case, the Timer Area).
Page 931 File Memory Instructions Section 3-26 Operand Specifications Area CIO Area CIO 0000 to CIO 0000 to CIO 0000 to CIO 6143 CIO 6143 CIO 6140 Work Area W000 to W000 to W000 to W511 W511 W508 Holding Bit Area H000 to H511 H000 to 508 H000 to H511 Auxiliary Bit Area A000 to A959...
Page 932 File Memory Instructions Section 3-26 The following table shows relevant flags in the Auxiliary Area. Name Address Operation Memory Card Type A34300 to Contains a binary number indicating the type A34302 of Memory Card, if any, that is installed. (0: None, 4: Flash ROM) Memory Card Format A34307 ON when the Memory Card is not formatted or...
Page 933 File Memory Instructions Section 3-26 The File Write Error Flag (A34308) will be turned ON and the instruction won’t be executed if the specified file isn’t the correct data type or the file data has been corrupted. A few seconds is required for the CPU Unit to detect a Memory Card after it has been inserted.
Page 934: Display Instructions: Display Message: Msg(046)
Display Instructions: DISPLAY MESSAGE: MSG(046) Section 3-27 Converted to ASCII I/O memory 1234 8 bytes (higher-addressed word first in field) 5678 56781234,DEF09ABC 9ABC DEF0 Delimiter File Displayed as Text Data Contents of ABC.CSV Examples When CIO 000000 turns ON in the following example, FWRIT(701) reads 10 words of data from D00400 through D00409 and uses that data to overwrite 10 words in file \ABC\XYZ.IOM starting at the beginning of the file + 5 words.
Page 935 Display Instructions: DISPLAY MESSAGE: MSG(046) Section 3-27 Variations Variations Executed Each Cycle for ON Condition MSG(046) Executed Once for Upward Differentiation @MSG(046) Executed Once for Downward Differentiation Not supported. Immediate Refreshing Specification Not supported. Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks...
Page 936 Display Instructions: DISPLAY MESSAGE: MSG(046) Section 3-27 After a message has been registered, the message display can be changed by overwriting the message in the message storage area. To clear a message that has been registered, execute MSG(046) with S set to the message number of the message you want to clear and N set to a con- stant (0000 to FFFF).
Page 937: Clock Instructions
Clock Instructions Section 3-28 ASCII Four leftmost bits 3-28 Clock Instructions This section describes instructions used with the system clock. Instruction Mnemonic Function code Page CALENDAR ADD CADD CALENDAR SUBTRACT CSUB HOURS TO SECONDS SECONDS TO HOURS CLOCK ADJUSTMENT DATE 3-28-1 CALENDAR ADD: CADD(730) Purpose Adds time to the calendar data in the specified words.
Page 938 Clock Instructions Section 3-28 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands C through C+2: Calendar Data Set the calendar data in C through C+2 as shown in the following diagram. C through C+2 must be in the same data area. Seconds: 00 to 59 (BCD) Minutes: 00 to 59 (BCD) Hour: 00 to 23 (BCD)
Page 939 Clock Instructions Section 3-28 R through R+2: Result Data R through R+2 contain the result of the addition. R through R+2 must be in the same data area. Seconds: 00 to 59 (BCD) Minutes: 00 to 59 (BCD) Hour: 00 to 23 (BCD) Day: 01 to 31 (BCD) Month: 01 to 12 (BCD) Year: 00 to 99 (BCD)
Page 940 Clock Instructions Section 3-28 Area Index Registers – Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR005+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description CADD(730) adds the calendar data (words C through C+2) to the time data (words T and T+1) and outputs the resulting calendar data to R through R+2.
Page 941 Clock Instructions Section 3-28 3-28-2 CALENDAR SUBTRACT: CSUB(731) Purpose Subtracts time from the calendar data in the specified words. Ladder Symbol CSUB(731) C: First calendar word T: First time word R: First result word Variations Variations Executed Each Cycle for ON Condition CSUB(731) Executed Once for Upward Differentiation @CSUB(731)
Page 942 Clock Instructions Section 3-28 T and T+1: Time Data Set the time data in T and T+1 as shown in the following diagram. T and T+1 must be in the same data area. Seconds: 00 to 59 (BCD) Minutes: 00 to 59 (BCD) Hours: 0000 to 9999 (BCD) R through R+2: Result Data R through R+2 contain the result of the addition.
Page 943 Clock Instructions Section 3-28 Area EM Area without bank E00000 to E00000 to E00000 to E32765 E32766 E32765 EM Area with bank En_00000 to En_00000 to En_00000 to En_32765 En_32766 3En_2765 (n = 0 to C) (n = 0 to C) (n = 0 to C) Indirect DM/EM @D00000 to @D32767...
Page 944 Clock Instructions Section 3-28 18:30:20 10 July, 1998 50 hours, 10 minutes, 15 seconds 16:20:05 8 July, 1998 3-28-3 HOURS TO SECONDS: SEC(065) Purpose Converts time data in hours/minutes/seconds format to an equivalent time in seconds only. Ladder Symbol SEC(065) S: First source word D: First destination word Variations...
Page 945 Clock Instructions Section 3-28 D and D+1: Result Data D and D+1 contain the result data in seconds-only format. D and D+1 must be in the same data area. Rightmost 4 digits Seconds: 0000 to 9999 (BCD) Leftmost 4 digits Seconds: 0000 to 3599 (BCD) Operand Specifications Area...
Page 946 Clock Instructions Section 3-28 Description SEC(065) converts the 8-digit BCD hours/minutes/seconds data in S and S+1 to 8-digit BCD seconds-only data and outputs the result to D and D+1. Minutes Seconds Hours Seconds Flags Name Label Operation Error Flag ON if the minutes data in S (bits 08 to 15) is not BCD and in the range 00 to 59.
Page 947 Clock Instructions Section 3-28 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Operands S and S+1: Source Data Set the seconds source data in S and S+1, as shown in the following diagram. S and S+1 must be in the same data area. Rightmost 4 digits Seconds: 0000 to 9999 (BCD) Leftmost 4 digits...
Page 948 Clock Instructions Section 3-28 Area Indirect DM/EM *D00000 to *D32767 addresses in BCD *E00000 to *E32767 *En_00000 to *En_32767 (n = 0 to C) Constants 00000000 to 35999999 (BCD) Data Registers Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++)
Page 949 Clock Instructions Section 3-28 3-28-5 CLOCK ADJUSTMENT: DATE(735) Purpose Changes the internal clock setting to the setting in the specified source words. Note The internal clock setting can also be changed from a Peripheral Device or the CLOCK WRITE FINS command (0702). Ladder Symbol DATE(735) S: First source word...
Page 950 Clock Instructions Section 3-28 The following table shows the structure of the Calendar/Clock Area. Addresses Contents A35100 to A35107 Second (00 to 59, BCD) A35108 to A35115 Minute (00 to 59, BCD) A35200 to A35207 Hour (00 to 23, BCD) A35208 to A35215 Day of month (01 to 31, BCD) A35300 to A35307...
Page 951: Debugging Instructions
Debugging Instructions Section 3-29 Flags Name Label Operation Error Flag ON if the new clock setting in S through S+3 isn’t within the specified range. OFF in all other cases. Precautions An error will not be generated even if the internal clock is set to a non-existent date (such as November 31).
Page 952 Debugging Instructions Section 3-29 Memory. The trace ends when the Trace Memory is full. The contents of Trace Memory can be monitored from a Peripheral Device when necessary. PC data area TRSM(045) executed. Specified bit or word Data sampling Trace Memory Tracing ends when Trace Memory is full.
Page 953 Debugging Instructions Section 3-29 a) Set the address of the bit or word to be traced. b) Set the trigger condition. One of the three following conditions can con- trol when data stored into Trace Memory is valid. i) The Trace Start Bit goes from OFF to ON. ii) A specified bit goes from OFF to ON.
Page 954 Debugging Instructions Section 3-29 Precautions TRSM(045) is processed as NOP(000) when data tracing is not being per- formed or when the sampling interval set in the parameters with a Peripheral Device is not set to sample on TRSM(045) instruction execution. Do not turn the Sampling Start Bit (A50815) ON or OFF from the program.
Page 955: Failure Diagnosis Instructions
Failure Diagnosis Instructions Section 3-30 3-30 Failure Diagnosis Instructions This section describes instructions used to define and handle errors. Instruction Mnemonic Function code Page FAILURE ALARM SEVERE FAILURE ALARM FALS FAILURE POINT DETECTION 3-30-1 FAILURE ALARM: FAL(006) Purpose Generates or clears user-defined non-fatal errors. Non-fatal errors do not stop PLC operation.
Page 956 Failure Diagnosis Instructions Section 3-30 Note The value of operand N must be different from the content of A529 (the system-generated FAL/FALS number). Function #0001 to #01FF Clears the non-fatal error with the correspond- ing FAL number. #FFFF Clears all non-fatal errors. Other* Clears the most serious non-fatal error.
Page 957 Failure Diagnosis Instructions Section 3-30 Area Index Registers Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 ,IR0+(++) to ,IR15+(++) ,–(– –)IR0 to, –(– –)IR15 Description The operation of FAL(006) depends on the value of N.
Page 958 Failure Diagnosis Instructions Section 3-30 Displaying Messages with Non-fatal User-defined Errors If S is a word address and an ASCII message has been stored at S, that mes- sage will be displayed at the Peripheral Device when FAL(006) is executed. (If a message isn’t required, set S to a constant.) The message beginning at S will be registered when FAL(006) is executed.
Page 959 Failure Diagnosis Instructions Section 3-30 FALS/FPD instructions more than once with the same values in A529 and N, but different values in S and S+1. 3. If a more serious error (including a system-generated fatal error or FALS(007) error) occurs at the same time as the FAL(006) instruction, the more serious error’s error code will be written to A400.
Page 960 Failure Diagnosis Instructions Section 3-30 and the Error Log is becoming full of user-defined FAL(006) errors. The follow- ing table shows the PLC Setup setting: Item Setting Programming Console Word setting address Name FAL Error Log Registration Settings 0: Record FAL Errors in Error Log. 1: Do not record FAL Errors in Error Log.
Page 961 Failure Diagnosis Instructions Section 3-30 The following tables show relevant words and flags in the Auxiliary Area. • Auxiliary Area Words/Flags for User-defined Errors Only Name Address Operation FAL Error Flag A40215 ON when an error is generated with FAL(006). Executed FAL Num- A36001 to When an error is generated with FAL(006),...
Page 962 Failure Diagnosis Instructions Section 3-30 MESSAGE LOW VOLTAGE Clearing a Particular Non-fatal Error When CIO 000001 is ON in the following example, FAL(006) will clear the non-fatal error with FAL number 31, turn OFF the corresponding Executed FAL Number Flag (A36114), and turn OFF the FAL Error Flag (A40215). 000001 Set N to 0 to clear errors #001F...
Page 963 Failure Diagnosis Instructions Section 3-30 3. The CPU Bus Unit Setup Error Flag (A40203) and CPU Bus Unit Setup Er- ror Flag for unit number 1 (A42701) will be turned ON. 4. The CPU Unit’s ERR Indicator will flash. 5. A message (CPU BU ST ERR 01) will be displayed at the Programming Console indicating that an error has occurred with CPU Bus Unit 1.
Page 964 Failure Diagnosis Instructions Section 3-30 Operands Generating User-defined Fatal Errors The following table shows the function of the operands. Note The value of operand N must be different from the content of A529 (the system-generated FAL/FALS number). Operand Function 1 to 511 (These FALS numbers are shared with FAL numbers.) Specifies the first of eight words containing an ASCII message to be displayed on the Programming Device.
Page 965 Failure Diagnosis Instructions Section 3-30 Description FALS(007) generates a fatal error. In CS1-H, CJ1-H, CJ1M, and CS1D CPU Units, FALS(007) can also be used to generate fatal system errors as well as fatal user-defined errors. (A system error will be generated if the value of N equals the content of A529.) Generating Fatal User-defined Errors When FALS(007) is executed with N set to an FALS number (1 to 511) that is...
Page 966 Failure Diagnosis Instructions Section 3-30 Generating Non-fatal System Errors (CS1-H, CJ1-H, CJ1M, or CS1D Only) Error code written to A400 Execution of FALS(007) Error code and time written to Error Log Area FALS generates a fatal system error with the error The corresponding Auxiliary Area Flags are set code/details specified in based on the error code and error details.
Page 967 Failure Diagnosis Instructions Section 3-30 Note Unlike user-defined fatal errors, system errors generated by FALS(007) will clear I/O memory if the IOM Hold Bit is OFF. The following areas will be cleared: CIO Area, Work Area, Timer Flags and PVs, Index Registers, and Data registers.
Page 968 Failure Diagnosis Instructions Section 3-30 Error name Error code Error details Too Many I/O 80E1 Hex Bits 13 to 15: Error Cause Points Error Bits 00 to 12: Details • Total number of I/O points is too high. Bits 13 to 15: 000 Bits 00 to 12: Number of I/O points (binary) •...
Page 969 Failure Diagnosis Instructions Section 3-30 Flags Name Label Operation Error Flag ON if N isn’t within the specified range of 0001 to 01FF (1 to 511 decimal). ON if a fatal system error is being generated (CS1-H/CJ1- H/CJ1M/CS1D Only), but the specified error code or error details code is incorrect.
Page 970 Failure Diagnosis Instructions Section 3-30 MESSAGE LOW VOLTAGE Generating a Non-fatal System Error (CS1-H, CJ1-H, CJ1M, and CS1D CPU Units Only) When CIO 000000 is ON in the following example, FALS(007) will generate a Too Many I/O Points Error (too many Expansion Racks connected, 9 Racks in this case).
Page 971 Failure Diagnosis Instructions Section 3-30 3-30-3 FAILURE POINT DETECTION: FPD(269) Purpose Diagnoses a failure in an instruction block by monitoring the time between execution of FPD(269) and execution of a diagnostic output and finding which input is preventing an output from being turned ON. Ladder Symbol FPD(269) C: Control word...
Page 972 Failure Diagnosis Instructions Section 3-30 Area EM Area with bank En_00000 to En_32767 (n = 0 to C) Indirect DM/EM @ D00000 to @ D32767 addresses in binary @ E00000 to @ E32767 @ En_00000 to @ En_32767 (n = 0 to C) Indirect DM/EM *D00000 to *D32767 addresses in BCD...
Page 973 Failure Diagnosis Instructions Section 3-30 Time Monitoring Function FPD(269) starts timing when it is executed (when execution condition A goes ON); it will generate a non-fatal error and turn ON the Carry Flag if the diag- nostic output isn’t turned ON within the specified monitoring time. Execution condition for FPD(269) Monitoring...
Page 974 Failure Diagnosis Instructions Section 3-30 The logic diagnosis function is executed every cycle as long as the execution condition for FPD(269) is ON. The operation of the logic diagnosis function is independent of the time monitoring function. When two or more input bits are preventing the diagnostic output from being turned ON, the address of the first input bit in the execution condition (on the highest instruction line and nearest the left bus bar) will be output to R+2 through R+4.
Page 975 Failure Diagnosis Instructions Section 3-30 Not possible to use. Input type 0: Normally open 1: Normally closed Bit Address Found Flag 0: Not found yet 1: Bit address found Not possible to use. Bit Address and Message Output (C=8@@@) When the leftmost digit of C is set to 8, the ASCII address of the input bit is output to R+2 to R+4.
Page 976 Failure Diagnosis Instructions Section 3-30 Register words R+2 through R+5 would have the following values for W51115: Word Bits 8 to 15 Bits 0 to 7 2D (hexadecimal) Input type (hexadecimal) 30: Normally open 31: Normally closed The user can store an ASCII message in register words R+6 to R+10. This message will be displayed on the Programming Device if a non-fatal error is generated by the time monitoring function.
Page 977 Failure Diagnosis Instructions Section 3-30 Setting Monitoring Time If a word address is specified for T, the monitoring time can be set automati- cally with the teaching function. Use the following procedure when a word with the Teaching Function address has been set for T. 1,2,3...
Page 978 Failure Diagnosis Instructions Section 3-30 Examples The following program example is used to demonstrate the operation of the time monitoring function and logic diagnosis function. In this example, the diagnostic output (CIO 020000) doesn’t go ON because CIO 010000 and CIO 010003 remain OFF in the logic diagnosis execution condition.
Page 979 Failure Diagnosis Instructions Section 3-30 Logic Diagnosis Function (C=800A) Since the leftmost digit of C is 8 (bit address and message output mode) the address of CIO 010000 (010000) is output to D00302 through D00304 in ASCII. FAL number = 10 Diagnostic output mode = 8 (bit address and message output) Bit Address Found Flag Input type...
Page 980: Other Instructions
Other Instructions Section 3-31 FPD Teaching Bit A59800 Execution condition CIO 030000 No error generated. Diagnostic output CIO 020000 Measured time: t × 1.5) Teaching : Initial setting in T : Measured time t’ : New setting in T after teaching ×...
Page 981 Other Instructions Section 3-31 Flags Name Label Operation Error Flag OFF or unchanged (See note.) Equals Flag OFF or unchanged (See note.) Carry Flag Negative Flag OFF or unchanged (See note.) Note In CS1 and CJ1 CPU Units, these Flags are turned OFF. In CS1-H, CJ1-H, and CJ1M CPU Units, these Flags are left unchanged.
Page 982 Other Instructions Section 3-31 Note The +(400), +L(401), +B(404), +BL(405), –(410), –L(411), –B(414), and –BL(415) instructions do no include the Carry Flag in their addition and sub- traction operations. In general, use these instructions when performing addi- tion or subtraction. 3-31-3 SELECT EM BANK: EMBC(281) Purpose Changes the current EM bank.
Page 983 Other Instructions Section 3-31 Description EMBC(281) changes the current EM (Extended Data Memory) bank to the one indicated by the EM bank number (N). At the same time, the new EM bank number is output to A301. There are up to 13 banks (0 to C) available in the EM Area and there are 32,768 words (E00000 to E32767) in each bank.
Page 984 Other Instructions Section 3-31 3-31-4 EXTEND MAXIMUM CYCLE TIME: WDT(094) Purpose Extends the maximum cycle time, but only for the cycle in which the instruc- tion is executed. WDT(094) can be used to prevent errors for long cycle times when a longer cycle time is temporarily required for special processing. Ladder Symbol WDT(094) T: Timer setting...
Page 985 Other Instructions Section 3-31 The following table shows the watchdog timer settings in the PLC Setup. The default value for the maximum cycle time is 1,000 ms, although it can be set anywhere from 1 to 40,000 ms in 10-ms units. Name Function Settings...
Page 986 Other Instructions Section 3-31 3-31-5 SAVE CONDITION FLAGS: CCS(282) Saves the current status of the Condition Flags in a separate area within the CPU Unit. The current status of the Flags is preserved so that it can be read (restored) with CCL(283) at a different location in the program, in a different task, or even in a later cycle.
Page 987 Other Instructions Section 3-31 Within a task Between cyclic tasks Between cycles CCL(283) is executed to read the status in the next cycle after CCS(282) was executed to save the status. Note 1. The status of the Condition Flags cannot be saved/loaded between a cyclic task and interrupt task.
Page 988 Other Instructions Section 3-31 000000 When CIO 000000 is ON in the following example, CMP(020) will compare the D00000 contents of D00000 and D00300 and those D00300 results will be preserved by CCS(282). The preserved Condition Flags are restored by CCL(283). This MOV(021) instruction is executed if the result of the CMP(020) instruction caused the D00000...
Page 989 Other Instructions Section 3-31 Task Instruction A CCL(283) is used alone to clear the Condition Flags after execution of instruction A so that those results do not affect instruction B and later instructions. Instruction B Refer to 3-31-5 SAVE CONDITION FLAGS: CCS(282) for more examples showing how to use CCS(282) and CCL(283).
Page 990 Other Instructions Section 3-31 FRMCV D00000 D00000 #2001 1. The CV-series PLC memory address is converted to its equivalent CV-series data area address. CV-series PLC CV-series data memory address area address 2001 Hex D00001 2. The corresponding CV-series data area address is converted to its CS/CJ-series PLC memory address.
Page 991 Other Instructions Section 3-31 The FRMCV(284) instruction can be used to convert a CV-series program with the following two kinds of programming for use in a CS/CJ-series PLC. See the Examples later in this section for an example. 1. When using indirect binary mode DM addressing (*DM) (when indirectly specifying a data area address with a PLC memory ad- dress in DM) 2.
Page 992 Other Instructions Section 3-31 Example 1: Converting a CV-series Program with *DM Indirect Binary Examples Mode DM Addressing In this FRMCV(284) example, a DM word is specified in S, the PLC memory address there is stored in an Index Register, and the Index Register is used for indirectly addressed.
Page 993 Other Instructions Section 3-31 Example 2: Converting a CV-series Program with PLC Memory Addresses Stored directly in Index Registers In this FRMCV(284) example, the CV-series PLC memory address is speci- fied directly in S. • CV-series program • CS/CJ-series program (Program using PLC memory addresses stored directly in IR) 000000...
Page 994 Other Instructions Section 3-31 Applicable Program Areas Block program areas Step program areas Subroutines Interrupt tasks Description When the execution condition is ON, TOCV(285) executes the following oper- ations. 1. The CS/CJ-series PLC memory address specified in S is converted to its equivalent CS/CJ-series data area address.
Page 995 Other Instructions Section 3-31 Data area address CS/CJ-series PLC memory address 0000CH 0C000Hex 0001CH 0C001Hex D00000 10000Hex Convert D00001 10001Hex Specify the CS/CJ-series PLC memory address in S. EC_32767 FFFFFHex (In this case, 10001 Hex is the PLC memory address of D00001.) CV-series Corresponding...
Page 996 Other Instructions Section 3-31 Area Index Registers IR0 to IR15 Indirect addressing ,IR0 to ,IR15 using Index Registers –2048 to +2047 ,IR0 to –2048 to +2047 ,IR15 DR0 to DR15, IR0 to IR15 Note 1. An error will occur and the Error Flag will be turned ON if S specifies one of the following PLC memory addresses that do not exist in the CV-series: Area or addresses PLC memory addresses...
Page 997 Other Instructions Section 3-31 • CS/CJ-series program • CS/CJ-series program • CV-series program (Program using indirect Index Register addressing) 000000 000001 000000 TOCV #1234 #1234 ,IR0 *D00200 D00200 Transfer contents In this case, IR0 contains 10001 Hex. In this case, IR0 contains 10001 Hex. The of D00200 to CV- Since the data area address data area address corresponding to PLC...
Page 998 Other Instructions Section 3-31 • RS-232C Port servicing • Event servicing with Inner Boards (CS-series only) • Event servicing (including background instruction processing) that uses a communications port number, i.e., an internal logical port. Execution condition Disables execution of IOSP peripheral servicing.
Page 999: Block Programming Instructions
Block Programming Instructions Section 3-32 3-31-10 ENABLE PERIPHERAL SERVICING: IORS(288) (CS1-H/CJ1-H/ CJ1M Only) Purpose Enables the peripheral servicing during program execution in Parallel Pro- cessing Mode that was disabled by IOSP(287), the DISABLE PERIPHERAL SERVICING instruction. This instruction is supported by the CS1-H, CJ1-H, and CJ1M CPU Units only. Ladder Symbol IORS(288) Variations...
Page 1000 Block Programming Instructions Section 3-32 Instruction Mnemonic Function code Page HIGH-SPEED TIMER WAIT TMHW (BCD) 1004 TMHWX (binary) LOOP LOOP 1007 LOOP END (NOT) LEND (NOT) 1007 3-32-1 Introduction Block Programs Up to 128 block programs within the overall user program (all tasks) with the CS/CJ-series.
Page 1001 Block Programming Instructions Section 3-32 Tasks and Block Programs Block programs can be located within tasks. While tasks are used to divide large programming units, block programs can be used within tasks to further divide programming into smaller units controlled with a single ladder diagram execution condition.
Page 1002 Block Programming Instructions Section 3-32 Execution Execution condition condition ON? "A" executed (be- tween IF and IEND). If execution is to wait until an execution condition or bit is ON (e.g., for step progressions), then WAIT(805) is used. If execution is to wait until for a specified period of time (e.g., for timed step progressions), then TIMW(813), TIMX(816), TMHW(815), or TMHWX(817) is used.
Page 1003 Block Programming Instructions Section 3-32 Mnemonic Name AND TST/TST NOT AND Bit Test Instructions OR TST/TST NOT OR Bit Test Instructions >$, <$,=$, >=$, <=$, <>$ Text String Comparison Instruction Good Example Bad Example Cannot be Used as used as execution execution condition...

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