General Configuration And Description; Physical Access - Texas Instruments LM5066I EVM User Manual

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3

General Configuration and Description

3.1

Physical Access

Table 2 lists the LM5066IEVM-626 connector and functionality,
availability, and Table 4
Connector
J1
J2
J3
J4
J5
Test Point
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15, TP19, TP20, TP21
TP16
TP17
TP18
TP22
TP23
TP24
TP25
TP26
TP27
SNVU444 – May 2014
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describes the switch functionality.
Table 2. Connector Functionality
Label
VIN Power bus input. Apply bus input voltage between J1 and J2.
GND Power bus input return connector. Apply bus input voltage between J1 and J2.
VOUT Switched bus output. Apply the load between J3 and J4.
GND Switch bus output return connector. Apply the load between J3 and J4.
PMBus interface
Table 3. Test Points
Label
VIN
VINK
SENSEK
SENSEK
GATE
VOUT_S
VOUT
FB
PG
TIMER
VREF
VAUX
EN
OVLO
GND
SDA
SCL
SMBA
VDD
RETRYB
CL
ADR0
ADR1
ADR2
Copyright © 2014, Texas Instruments Incorporated
General Configuration and Description
Table 3 describes the test point
Description
Description
Positive supply input
Positive supply Kelvin sense pin on sense resistor
Sense Kelvin sense pin on sense resistor
Sense pin test point
Gate drive output
Output voltage at the pass FET
Output voltage at the load
Power Good feedback
Power Good indicator
Timing capacitor voltage
Internal reference voltage
Auxiliary ADC input
UVLO/EN pin voltage
OVLO pin voltage
Circuit ground
SMBus input/output
SMBis clock
SMBUS alert line (active low)
Internal sub-regulator 4.85-V output
Fault retry input
Current limit range
SMBus address line 0
SMBus address line 1
SMBus address line 2
LM5066IEVM-626 Evaluation Module (EVM)
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