Timb Counter Prescaler; Input Capture - Freescale Semiconductor MC68HC908MR16 Datasheet

Timer Interface B (TIMB)
Addr. Register Name
TIMB Channel 0 Status/Control
$0056
(TBSC0) See page 247.
TIMB Channel 0 Register High
$0057
See page 250.
TIMB Channel 0 Register Low
$0058
See page 250.
TIMB Channel 1 Status/Control
$0059
(TBSC1) See page 247.
TIMB Channel 1 Register High
$005A
See page 250.
TIMB Channel 1 Register Low
$005B
See page 250.

17.3.1 TIMB Counter Prescaler

The TIMB clock source can be one of the seven prescaler outputs or the TIMB clock pin,
The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIMB status and control register select the TIMB clock source.

17.3.2 Input Capture

An input capture function has three basic parts:
1. Edge select logic
2. Input capture latch
3. 16-bit counter
Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector senses a defined transition. The
polarity of the active edge is programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in TBSC0–TBSC1 control registers with
x referring to the active channel number). When an active edge occurs on the pin of an input capture
channel, the TIMB latches the contents of the TIMB counter into the TIMB channel registers,
TCHxH–TCHxL. Input captures can generate TIMB CPU interrupt requests. Software can determine that
an input capture event has occurred by enabling input capture interrupts or by polling the status flag bit.
The free-running counter contents are transferred to the TIMB channel status and control register
(TBCHxH–TBCHxL, see
238
Bit 7
Read: CH0F
Register Write: 0
Reset: 0
Read:
Bit 15
(TBCH0H) Write:
Reset:
Read:
Bit 7
(TBCH0L) Write:
Reset:
Read: CH1F
Register Write: 0
Reset: 0
Read:
Bit 15
(TBCH1H) Write:
Reset:
Read:
Bit 7
(TBCH1L) Write:
Reset:
R = Reserved
Figure 17-3. TIMB I/O Register Summary (Continued)
17.7.5 TIMB Channel
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
6 5 4
CH0IE MS0B MS0A
0 0 0
Bit 14 Bit 13 Bit 12
Indeterminate after reset
Bit 6 Bit 5 Bit 4
Indeterminate after reset
0
CH1IE MS1A
R
0 0 0
Bit 14 Bit 13 Bit 12
Indeterminate after reset
Bit 6 Bit 5 Bit 4
Indeterminate after reset
Registers) on each proper signal transition regardless of
3 2 1
ELS0B ELS0A TOV0
0 0 0
Bit 11 Bit 10 Bit 9
Bit 3 Bit 2 Bit 1
ELS1B ELS1A TOV1
0 0 0
Bit 11 Bit 10 Bit 9
Bit 3 Bit 2 Bit 1
PTE0/TCLKB
Freescale Semiconductor
Bit 0
CH0MAX
0
Bit 8
Bit 0
CH1MAX
0
Bit 8
Bit 0
.