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Memory
Addr.
Register Name
TIMA Channel 2 Register High
$001A
See page 232.
TIMA Channel 2 Register Low
$001B
See page 232.
TIMA Channel 3 Status/Control
$001C
Register (TASC3)
See page 229.
TIMA Channel 3 Register High
$001D
See page 232.
TIMA Channel 3 Register Low
$001E
See page 232.
Configuration Register
$001F
See page 74.
PWM Control Register 1
$0020
See page 146.
PWM Control Register 2
$0021
See page 148.
Fault Control Register
$0022
See page 150.
Fault Status Register
$0023
See page 152.
Fault Acknowledge Register
$0024
See page 153.
PWM Output Control Register
$0025
See page 154.
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 8)
30
Bit 7
Read:
Bit 15
(TACH2H)
Write:
Reset:
Read:
Bit 7
(TACH2L)
Write:
Reset:
Read:
CH3F
Write:
0
Reset:
0
Read:
Bit 15
(TACH3H)
Write:
Reset:
Read:
Bit 7
(TACH3L)
Write:
Reset:
Read:
EDGE
(CONFIG)
Write:
Reset:
0
Read:
DISX
(PCTL1)
Write:
Reset:
0
Read:
LDFQ1
(PCTL2)
Write:
Reset:
0
Read:
FINT4
(FCR)
Write:
Reset:
0
Read: FPIN4
(FSR)
Write:
Reset:
U
Read:
0
(FTACK)
Write:
Reset:
0
Read:
0
(PWMOUT)
Write:
Reset:
0
R
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
6
5
4
Bit 14
Bit 13
Bit 12
Indeterminate after reset
Bit 6
Bit 5
Bit 4
Indeterminate after reset
0
CH3IE
MS3A
R
0
0
0
Bit 14
Bit 13
Bit 12
Indeterminate after reset
Bit 6
Bit 5
Bit 4
Indeterminate after reset
BOTNEG TOPNEG
INDEP
0
0
0
DISY
PWMINT
PWMF
0
0
0
0
LDFQ0
IPOL1
0
0
0
FMODE4
FINT3
FMODE3
0
0
0
FFLAG4
FPIN3
FFLAG3
0
U
0
0
DT6
DT5
FTACK4
FTACK3
0
0
0
OUTCTL
OUT6
OUT5
0
0
0
= Reserved
Bold
3
2
1
Bit 11
Bit 10
Bit 9
Bit 3
Bit 2
Bit 1
ELS3B
ELS3A
TOV3
0
0
0
Bit 11
Bit 10
Bit 9
Bit 3
Bit 2
Bit 1
LVIRST
LVIPWR
STOPE
1
1
0
ISENS1
ISENS0
LDOK
0
0
0
IPOL2
IPOL3
PRSC1
0
0
0
FINT2
FMODE2
FINT1
0
0
0
FPIN2
FFLAG2
FPIN1
U
0
U
DT4
DT3
DT2
FTACK2
0
0
0
OUT4
OUT3
OUT2
0
0
0
= Buffered
= Unimplemented
Freescale Semiconductor
Bit 0
Bit 8
Bit 0
CH3MAX
0
Bit 8
Bit 0
COPD
0
PWMEN
0
PRSC0
0
FMODE1
0
FFLAG1
0
DT1
FTACK1
0
OUT1
0
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