Sci Control Register 2 - Freescale Semiconductor MC68HC908MR16 Datasheet

Control Bits
M
0
1
0
0
1
1

13.7.2 SCI Control Register 2

SCI control register 2 (SCC2):
• Enables these CPU interrupt requests:
– Enables the SCTE bit to generate transmitter CPU interrupt requests
– Enables the TC bit to generate transmitter CPU interrupt requests
– Enables the SCRF bit to generate receiver CPU interrupt requests
– Enables the IDLE bit to generate receiver CPU interrupt requests
• Enables the transmitter
• Enables the receiver
• Enables SCI wakeup
• Transmits SCI break characters
Address: $0039
Read:
SCTIE
Write:
Reset:
SCTIE — SCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate SCI transmitter CPU interrupt requests. Setting
the SCTIE bit in SCC3 enables SCTE CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate SCI transmitter CPU interrupt requests. Reset clears
the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
Freescale Semiconductor
Table 13-4. Character Format Selection
Start
PEN:PTY
Bits
0X 1
0X 1
10 1
11 1
10 1
11 1
Bit 7 6 5
TCIE SCRIE
0 0 0
Figure 13-9. SCI Control Register 2 (SCC2)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Character Format
Data Stop
Parity
Bits Bits
8 None 1
9 None 1
7 Even 1
7 Odd 1
8 Even 1
8 Odd 1
4 3 2
ILIE TE RE
0 0 0
I/O Registers
Character
Length
10 bits
11 bits
10 bits
10 bits
11 bits
11 bits
1 Bit 0
RWU SBK
0 0
171