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Memory
Addr.
Register Name
TIMB Counter Register Low
$0053
See page 246.
TIMB Counter Modulo Register
$0054
High (TBMODH)
See page 246.
TIMB Counter Modulo Register
$0055
Low (TBMODL)
See page 246.
TIMB Channel 0 Status/Control
$0056
Register (TBSC0)
See page 247.
TIMB Channel 0 Register High
$0057
See page 250.
TIMB Channel 0 Register Low
$0058
See page 250.
TIMB Channel 1 Status/Control
$0059
Register (TBSC1)
See page 247.
TIMB Channel 1 Register High
$005A
See page 250.
TIMB Channel 1 Register Low
$005B
See page 250.
PLL Control Register
$005C
See page 66.
PLL Bandwidth Control
$005D
Register (PBWC)
See page 67.
PLL Programming Register
$005E
See page 68.
$005F
Unimplemented
U = Unaffected
X = Indeterminate
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 8)
34
Bit 7
Read:
Bit 7
(TBCNTL)
Write:
R
Reset:
0
Read:
Bit 15
Write:
Reset:
1
Read:
Bit 7
Write:
Reset:
1
Read:
CH0F
Write:
0
Reset:
0
Read:
Bit 15
(TBCH0H)
Write:
Reset:
Read:
Bit 7
(TBCH0L)
Write:
Reset:
Read:
CH1F
Write:
0
Reset:
0
Read:
Bit 15
(TBCH1H)
Write:
Reset:
Read:
Bit 7
(TBCH1L)
Write:
Reset:
Read:
PLLIE
(PCTL)
Write:
Reset:
0
Read:
AUTO
Write:
Reset:
0
Read:
MUL7
(PPG)
Write:
Reset:
0
R
= Reserved
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
6
5
4
Bit 6
Bit 5
Bit 4
R
R
R
0
0
0
Bit 14
Bit 13
Bit 12
1
1
1
Bit 6
Bit 5
Bit 4
1
1
1
CH0IE
MS0B
MS0A
0
0
0
Bit 14
Bit 13
Bit 12
Indeterminate after reset
Bit 6
Bit 5
Bit 4
Indeterminate after reset
0
CH1IE
MS1A
R
0
0
0
Bit 14
Bit 13
Bit 12
Indeterminate after reset
Bit 6
Bit 5
Bit 4
Indeterminate after reset
PLLF
PLLON
BCS
R
0
1
0
LOCK
ACQ
XLD
R
0
0
0
MUL6
MUL5
MUL4
1
1
0
Bold
3
2
1
Bit 3
Bit 2
Bit 1
R
R
R
0
0
0
Bit 11
Bit 10
Bit 9
1
1
1
Bit 3
Bit 2
Bit 1
1
1
1
ELS0B
ELS0A
TOV0
0
0
0
Bit 11
Bit 10
Bit 9
Bit 3
Bit 2
Bit 1
ELS1B
ELS1A
TOV1
0
0
0
Bit 11
Bit 10
Bit 9
Bit 3
Bit 2
Bit 1
1
1
1
R
R
R
1
1
1
0
0
0
R
R
R
0
0
0
VRS7
VRS6
VRS5
0
1
1
= Buffered
= Unimplemented
Freescale Semiconductor
Bit 0
Bit 0
R
0
Bit 8
1
Bit 0
1
CH0MAX
0
Bit 8
Bit 0
CH1MAX
0
Bit 8
Bit 0
1
R
1
0
R
0
VRS4
0
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