Serial Peripheral Interface Characteristics - Freescale Semiconductor MC68HC908MR16 Datasheet

19.8 Serial Peripheral Interface Characteristics

Diagram
(1)
Number
Operating frequency
Master
Slave
Cycle time
1 Master
Slave
2 Enable lead time
3 Enable lag time
Clock (SPCK) high time
4 Master
Slave
Clock (SPCK) low time
5 Master
Slave
Data setup time (inputs)
6 Master
Slave
Data hold time (inputs)
7 Master
Slave
Access time, slave
8
CPHA = 0
CHPA = 1
9
Disable time, slave
Data valid time after enable edge
Master
10
(5)
Slave
1. V = 5.0 Vdc ± 10%, all timing is shown with respect to 20% V
DD
load on all SPI pins
2. Numbers refer to dimensions in
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
5. With 100 pF on all SPI pins
Freescale Semiconductor
(2)
Characteristic
(3)
(4)
Figure 19-1 and Figure
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Serial Peripheral Interface Characteristics
Symbol
f
OP(M)
f
OP(S)
t
CYC(M)
t
CYC(S)
t
Lead(S)
t
Lag(S)
t
SCKH(M)
t
SCKH(S)
t
SCKL(M)
t
SCKL(S)
t
SU(M)
t
SU(S)
t
H(M)
t
H(S)
t
A(CP0)
t
A(CP1)
t
DIS(S)
t
V(M)
t
V(S)
and 70% V , unless otherwise noted; assumes 100 pF
DD DD
19-2.
Min Max
/128 /2
f
f
OP
OP
f
dc
OP
2 128
1 —
15 —
15 —
100 —
50 —
100 —
50 —
45 —
5 —
0 —
15 —
0 40
0 20
— 25
— 10
— 40
Unit
MHz
t
CYC
ns
ns
ns
ns
ns
ns
ns
ns
ns
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