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Addr.
Register Name
TIMA Channel 2 Register High
$001A
See page 232.
TIMA Channel 2 Register Low
$001B
See page 232.
TIMA Channel 3 Status/Control
$001C
Register (TASC3)
See page 229.
TIMA Channel 3 Register High
$001D
See page 232.
TIMA Channel 3 Register Low
$001E
See page 232.
16.3 Functional Description
Figure 16-2
shows the TIMA structure. The central component of the TIMA is the 16-bit TIMA counter that
can operate as a free-running counter or a modulo up-counter. The TIMA counter provides the timing
reference for the input capture and output compare functions. The TIMA counter modulo registers,
TAMODH–TAMODL, control the modulo value of the TIMA counter. Software can read the TIMA counter
value at any time without affecting the counting sequence.
The four TIMA channels are programmable independently as input capture or output compare channels.
16.3.1 TIMA Counter Prescaler
The TIMA clock source can be one of the seven prescaler outputs or the TIMA clock pin, PTE3/TCLKA.
The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0],
in the TIMA status and control register select the TIMA clock source.
16.3.2 Input Capture
An input capture function has three basic parts:
1. Edge select logic
2. Input capture latch
3. 16-bit counter
Two 8-bit registers, which make up the 16-bit input capture register, are used to latch the value of the
free-running counter after the corresponding input capture edge detector senses a defined transition. The
polarity of the active edge is programmable. The level transition which triggers the counter transfer is
defined by the corresponding input edge bits (ELSxB and ELSxA in TASC0–TASC3 control registers with
Freescale Semiconductor
Bit 7
Read:
Bit 15
(TACH2H)
Write:
Reset:
Read:
Bit 7
(TACH2L)
Write:
Reset:
Read:
CH3F
Write:
0
Reset:
0
Read:
Bit 15
(TACH3H)
Write:
Reset:
Read:
Bit 7
(TACH3L)
Write:
Reset:
= Reserved
R
Figure 16-3. TIM I/O Register Summary (Continued)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
6
5
4
14
13
12
Indeterminate after reset
6
5
4
Indeterminate after reset
0
CH3IE
MS3A
R
0
0
0
14
13
12
Indeterminate after reset
6
5
4
Indeterminate after reset
Functional Description
3
2
1
11
10
9
3
2
1
ELS3B
ELS3A
TOV3
0
0
0
11
10
9
3
2
1
Bit 0
Bit 8
Bit 0
CH3MAX
0
Bit 8
Bit 0
219
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