Low-Power Mode; I/O Signals - Freescale Semiconductor MC68HC908MR16 Datasheet

Serial Peripheral Interface Module (SPI)
WRITE TO SPDR
SPTE
SPSCK
CPHA:CPOL = 1:0
MOSI
SPRF
READ SPSCR
READ SPDR
1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
2
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
3
AND CLEARING SPTE BIT.
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
5 BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
6 CPU READS SPSCR WITH SPRF BIT SET.

15.10 Low-Power Mode

The WAIT instruction puts the MCU in a low power-consumption standby mode.
The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module
registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can
bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power consumption by disabling the
SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt
requests by setting the error interrupt enable bit (ERRIE). See
Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit
data register in break mode does not initiate a transmission nor is this data transferred into the shift
register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.

15.11 I/O Signals

The SPI module has five I/O pins and shares four of them with a parallel I/O port. The pins are:
• MISO — Data received
• MOSI — Data transmitted
• SPSCK — Serial clock
• SS — Slave select
208
1 3
2
MSBBIT BIT BIT BIT
6 5 4 3
BYTE 1
Figure 15-12. SPRF/SPTE CPU Interrupt Timing
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
8
5
BIT BIT LSBMSBBIT BIT BIT BIT BIT
2 1 6 5 4 3
BYTE 2
4
6
7
7 CPU READS SPDR, CLEARING SPRF BIT.
8
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
15.7 Interrupts.
10
BIT LSBMSBBIT BIT BIT
2 1 6 5 4
BYTE 3
9
11
12
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