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Serial Peripheral Interface Module (SPI)
Addr.
Register Name
SPI Control Register
$0044
SPI Status and Control
$0045
Register (SPSCR)
SPI Data Register
$0046
15.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR, is set.
Configure the SPI modules as master or slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
before disabling the master SPI. See
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI
pin under the control of the serial clock. See
The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register.
See
15.12.2 SPI Status and Control
master also controls the shift register of the slave peripheral.
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's
MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that
SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation,
198
Bit 7
Read:
SPRIE
(SPCR)
Write:
See page 211.
Reset:
0
Read:
SPRF
Write:
R
See page 212.
Reset:
0
Read:
R7
(SPDR)
Write:
T7
See page 214.
Reset:
R
Figure 15-3. SPI I/O Register Summary
MASTER MCU
MISO
SHIFT REGISTER
MOSI
SPSCK
BAUD RATE
SS
GENERATOR
Figure 15-4. Full-Duplex Master-Slave Connections
Register. Through the SPSCK pin, the baud-rate generator of the
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
6
5
R
SPMSTR
CPOL
0
1
OVRF
MODF
ERRIE
R
0
0
R6
R5
R4
T6
T5
T4
Unaffected by reset
= Reserved
NOTE
15.12.1 SPI Control
Figure
15-4.
MISO
MOSI
SPSCK
SS
V
DD
4
3
2
CPHA
SPWOM
0
1
0
SPTE
MODFEN
R
R
0
1
0
R3
R2
T3
T2
Register.
SLAVE MCU
SHIFT REGISTER
Freescale Semiconductor
1
Bit 0
SPE
SPTIE
0
0
SPR1
SPR0
0
0
R1
R0
T1
T0
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