Freescale Semiconductor MC68HC908MR16 Datasheet page 72

Clock Generator Module (CGM)
The K factor in the equations is derived from internal PLL parameters. K
is configured in acquisition mode, and K
See 4.3.2.2 Acquisition and Tracking
The inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. See
, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆
cycles, n
ACQ
before exiting acquisition mode. A certain number of clock cycles, n
PLL is within the lock mode entry tolerance, ∆
multiple of n /f , and the acquisition to lock time, t
ACQ RDV
the average frequency over the entire measurement period must be within the specified tolerance, the
total time usually is longer than t
In manual mode, it is usually necessary to wait considerably longer than t
clock (see 4.3.3 Base Clock Selector
Influences on Reaction Time
72
is the K factor when the PLL is configured in tracking mode.
TRK
Modes.
t =
ACQ
t =
AL
t
Lock
4.3.2.3 Manual and Automatic PLL Bandwidth Modes
Lock
as calculated in the previous example.
Lock
Circuit) because the factors described in
may slow the lock time considerably.
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
⎛ ⎞
V
⎛ ⎞
8
DDA
⎜ ⎟
-------------- - -------------- -
⎝ ⎠
⎝ f ⎠ K
RDV ACQ
⎛ ⎞
V
⎛ ⎞
4
DDA
⎜ ⎟
-------------- - ------------- -
⎝ ⎠
⎝ ⎠
f K
RDV TRK
= t + t
ACQ AL
NOTE
TRK
. Therefore, the acquisition time, t
, is an integer multiple of n
AL
is the K factor when the PLL
ACQ
A certain number of clock
, is required to ascertain that the
, is an integer
ACQ
/f . Also, since
TRK RDV
before selecting the PLL
Lock
4.8.2 Parametric
Freescale Semiconductor
,
TRK