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PS[2:0] — Prescaler Select Bits
These read/write bits select either the
input to the TIMA counter as
16.7.2 TIMA Counter Registers
The two read-only TIMA counter registers contain the high and low bytes of the value in the TIMA counter.
Reading the high byte (TACNTH) latches the contents of the low byte (TACNTL) into a buffer. Subsequent
reads of TACNTH do not affect the latched TACNTL value until TACNTL is read. Reset clears the TIMA
counter registers. Setting the TIMA reset bit (TRST) also clears the TIMA counter registers.
If TACNTH is read during a break interrupt, be sure to unlatch TACNTL by
reading TACNTL before exiting the break interrupt. Otherwise, TACNTL
retains the value latched during the break.
Register Name and Address:
Read:
Write:
Reset:
Register Name and Address:
Read:
Write:
Reset:
Figure 16-6. TIMA Counter Registers (TACNTH and TACNTL)
Freescale Semiconductor
PTE3/TCLKA
Table 16-1
shows. Reset clears the PS[2:0] bits.
Table 16-1. Prescaler Selection
PS[2:0]
000
001
010
011
100
101
110
111
TACNTH — $000F
Bit 7
6
5
Bit 15
Bit 14
Bit 13
R
R
R
0
0
0
TACNTL — $0010
Bit 7
6
5
Bit 7
Bit 6
Bit 5
R
R
R
0
0
0
R
= Reserved
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
pin or one of the seven prescaler outputs as the
TIMA Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
PTE3/TCLKA
NOTE
4
3
2
Bit 12
Bit 11
Bit 10
R
R
R
0
0
0
4
3
2
Bit 4
Bit 3
Bit 2
R
R
R
0
0
0
I/O Registers
1
Bit 0
Bit 9
Bit 8
R
R
0
0
1
Bit 0
Bit 1
Bit 0
R
R
0
0
227
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