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Clock Generator Module (CGM)
OSC2
OSC1
SIMOSCEN
CGMRDV
PHASE
DETECTOR
LOCK
DETECTOR
LOCK
CGMVDV
Addr.
Register Name
PLL Control Register
$005C
PLL Bandwidth Control Register
$005D
PLL Programming Register
$005E
58
CRYSTAL OSCILLATOR
CGMRCLK
V
CGMXFC
DDA
LOOP
FILTER
PLL ANALOG
BANDWIDTH
CONTROL
AUTO
ACQ
MUL[7:4]
FREQUENCY
DIVIDER
Figure 4-1. CGM Block Diagram
Bit 7
Read:
PLLIE
(PCTL)
Write:
See page 66.
Reset:
0
Read:
AUTO
(PBWC)
Write:
See page 67.
Reset:
0
Read:
MUL7
(PPG)
Write:
See page 68.
Reset:
0
R
Figure 4-2. CGM I/O Register Summary
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
CLOCK
÷ 2
SELECT
CIRCUIT
BCS
V
SS
VRS[7:4]
VOLTAGE
CONTROLLED
OSCILLATOR
INTERRUPT
CONTROL
PLLIE
PLLF
CGMVCLK
6
5
4
PLLF
PLLON
BCS
R
0
1
0
LOCK
ACQ
XLD
R
0
0
0
MUL6
MUL5
MUL4
1
1
0
= Reserved
CGMXCLK
TO SIM
A
CGMOUT
TO SIM
B S*
*WHEN S = 1, CGMOUT = B
USER MODE
PTC2
MONITOR MODE
CGMINT
3
2
1
1
1
1
R
R
R
1
1
1
0
0
0
R
R
R
0
0
0
VRS7
VRS6
VRS5
0
1
1
Freescale Semiconductor
Bit 0
1
R
1
0
R
0
VRS4
0
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