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Chapter 9
Low-Voltage Inhibit (LVI)
9.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V
and can force a reset when the V
9.2 Features
Features of the LVI module include:
•
Programmable LVI reset
•
Programmable power consumption
•
Digital filtering of V
•
Selectable LVI trip voltage
9.3 Functional Description
Figure 9-1
shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to
monitor V
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when V
DD
falls below a voltage, V
V
and V
are determined by the TRPSEL bit in the LVISCR (see
LVRX
LVHX
LVIRST are in the configuration register (CONFIG). See
V
DD
LOW V
DD
DETECTOR
TRPSEL
FROM LVISCR
Freescale Semiconductor
voltage falls to the LVI trip voltage.
DD
pin level
DD
, and remains at or below that level for nine or more consecutive CGMXCLK.
LVRX
LVIPWR
FROM CONFIG
CPU CLOCK
V
V
> LVItrip = 0
DD
DIGITAL FILTER
V
< LVItrip = 1
DD
ANLGTRIP
Figure 9-1. LVI Module Block Diagram
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Chapter 5 Configuration Register
FROM CONFIG
LVIRST
DD
LVIOUT
Figure
9-2). LVIPWR and
(CONFIG).
LVI RESET
pin
DD
DD
97
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