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Register Name and Address:
Read:
Write:
Reset:
Register Name and Address:
Read:
Write:
Reset:
Register Name and Address:
Read:
Write:
Reset:
Register Name and Address:
Read:
Write:
Reset:
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an active edge occurs on
the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the
TIMA counter registers matches the value in the TIMA channel x registers.
When CHxIE = 1, clear CHxF by reading TIMA channel x status and control register with CHxF set,
and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is
complete, then writing 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to
inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
Freescale Semiconductor
TASC0 — $0013
Bit 7
6
5
CH0F
CH0IE
MS0B
0
0
0
0
TASC1 — $0016
Bit 7
6
5
CH1F
0
CH1IE
0
R
0
0
0
TASC2 — $0019
Bit 7
6
5
CH2F
CH2IE
MS2B
0
0
0
0
TASC3 — $001C
Bit 7
6
5
CH3F
0
CH3IE
0
R
0
0
0
R
= Reserved
Figure 16-8. TIMA Channel Status
and Control Registers (TASC0–TASC3)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
4
3
2
MS0A
ELS0B
ELS0A
0
0
0
4
3
2
MS1A
ELS1B
ELS1A
0
0
0
4
3
2
MS2A
ELS2B
ELS2A
0
0
0
4
3
2
MS3A
ELS3B
ELS3A
0
0
0
I/O Registers
1
Bit 0
TOV0
CH0MAX
0
0
1
Bit 0
TOV1
CH1MAX
0
0
1
Bit 0
TOV2
CH2MAX
0
0
1
Bit 0
TOV3
CH3MAX
0
0
229
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