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9.4 LVI Status and Control Register
The LVI status register (LVISCR) flags V
Address:
$FE0F
Read:
LVIOUT
Write:
Reset:
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
CGMXCLK cycles. See
V
DD
< V
V
LVRX
TRPSEL — LVI Trip Select Bit
This bit selects the LVI trip point. Reset clears this bit.
1 = 5 percent tolerance. The trip point and recovery point are determined by V
respectively.
0 = 10 percent tolerance. The trip point and recovery point are determined by V
respectively.
If LVIRST and LVIPWR are 0s, note that when changing the tolerance, LVI
reset will be generated if the supply voltage is below the trip point.
9.5 LVI Interrupts
The LVI module does not generate interrupt requests.
9.6 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode.
With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT
instruction.
Freescale Semiconductor
voltages below the V
DD
Bit 7
6
5
0
TRPSEL
R
R
0
0
0
R
= Reserved
Figure 9-3. LVI Status and Control Register (LVISCR)
Table
9-1. Reset clears the LVIOUT bit.
Table 9-1. LVIOUT Bit Indication
V
DD
At Level:
For Number of CGMXCLK Cycles:
> V
+ V
LVRX
LVHX
< V
V
DD
LVRX
< V
V
Between 32 & 40 CGMXCLK cycles
DD
LVRX
< V
V
DD
LVRX
< V
+ V
DD
LVRX
LVHX
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
LVRX
4
3
2
0
0
0
R
R
R
0
0
0
voltage falls below the V
DD
Any
< 32 CGMXCLK cycles
> 40 CGMXCLK cycles
Any
NOTE
LVI Status and Control Register
level
.
1
Bit 0
0
0
R
R
0
0
voltage for 32 to 40
LVRX
LVIOUT
0
0
0 or 1
1
Previous value
and V
LVR1
and V
LVR2
,
LVH1
,
LVH2
99
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