Chapter 10 Input/Output (I/O) Ports (Ports); Input/Output (I/O) Ports (Ports); Introduction - Freescale Semiconductor MC68HC908MR16 Datasheet

Chapter 10

Input/Output (I/O) Ports (PORTS)

10.1 Introduction

Thirty-seven bidirectional input-output (I/O) pins and seven input pins form six parallel ports. All I/O pins
are programmable as inputs or outputs.
When using the 56-pin package version:
• Set the data direction register bits in DDRC such that bit 1 is written to a logic 1 (along with any
other output bits on port C).
• Set the data direction register bits in DDRE such that bits 0, 1, and 2 are written to a logic 1 (along
with any other output bits on port E).
• Set the data direction register bits in DDRF such that bits 0, 1, 2, and 3 are written to a logic 1 (along
with any other output bits on port F).
Connect any unused I/O pins to an appropriate logic level, either V
V . Although PWM6–PWM1 do not require termination for proper
SS
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr. Register Name
Port A Data Register
$0000
See page 103.
Port B Data Register
$0001
See page 104.
Port C Data Register
$0002
See page 106.
Port D Data Register
$0003
See page 107.
Data Direction Register A
$0004
See page 103.
Freescale Semiconductor
Bit 7
Read:
PTA7
(PTA) Write:
Reset:
Read:
PTB7
(PTB) Write:
Reset:
Read: 0
(PTC) Write: R
Reset:
Read: 0
(PTD) Write: R
Reset:
Read:
DDRA7
(DDRA) Write:
Reset: 0
R
Figure 10-1. I/O Port Register Summary
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
NOTE
6 5 4
PTA6 PTA5 PTA4
Unaffected by reset
PTB6 PTB5 PTB4
Unaffected by reset
PTC6 PTC5 PTC4
Unaffected by reset
PTD6 PTD5 PTD4
R R R
Unaffected by reset
DDRA6 DDRA5 DDRA4
0 0 0
= Reserved
or
DD
3 2 1
PTA3 PTA2 PTA1
PTB3 PTB2 PTB1
PTC3 PTC2 PTC1
PTD3 PTD2 PTD1
R R R
DDRA3 DDRA2 DDRA1
0 0 0
= Unimplemented
Bit 0
PTA0
PTB0
PTC0
PTD0
R
DDRA0
0
101