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V
DD
RST
PA7
PA0
NOTES:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Wait 1 bit time before sending next byte.
264
4096 + 32 CGMXCLK CYCLES
24 BUS CYCLES
256 BUS CYCLES (MINIMUM)
FROM HOST
1
FROM MCU
Figure 18-13. Monitor Mode Entry Timing
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
1
3
1
2
3
1
Freescale Semiconductor
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