Freescale Semiconductor MC68HC908MR16 Datasheet page 202

Serial Peripheral Interface Module (SPI)
When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its
active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and
the start of the SPI transmission. See
derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and
SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since
the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower
SPSCK. This uncertainty causes the variation in the initiation delay shown in
no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
BUS
CLOCK
MOSI
SPSCK
CPHA = 1
SPSCK
CPHA = 0
SPSCK CYCLE
NUMBER
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
BUS
CLOCK
202
Figure 15-8
WRITE
INITIATION DELAY
TO SPDR
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 2;
EARLIEST LATEST
2 POSSIBLE START POINTS
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 8;
EARLIEST
8 POSSIBLE START POINTS
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 32;
EARLIEST
32 POSSIBLE START POINTS
WRITE
TO SPDR
SPSCK = INTERNAL CLOCK ÷ 128;
EARLIEST
128 POSSIBLE START POINTS
Figure 15-8. Transmission Start Delay (Master)
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
The internal SPI clock in the master is a free-running
MSB BIT 6
1 2
Figure 15-8. This delay is
BIT 5
3
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LATEST
LATEST
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