Freescale Semiconductor MC68HC908MR16 Datasheet page 90

Bit Manipulation Branch
DIR DIR REL DIR
MSB
0 1 2 3
LSB
5 4 3
0 BRSET0 BSET0 BRA NEG
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
1 BRCLR0 BCLR0 BRN CBEQ
3 DIR 2 DIR 2 REL 3 DIR
5 4 3
2 BRSET1 BSET1 BHI
3 DIR 2 DIR 2 REL
5 4 3
3 BRCLR1 BCLR1 BLS COM
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
4 BRSET2 BSET2 BCC LSR
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
5 BRCLR2 BCLR2 BCS STHX
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
6 BRSET3 BSET3 BNE ROR
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
7 BRCLR3 BCLR3 BEQ ASR
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
8 BRSET4 BSET4 BHCC LSL
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
9 BRCLR4 BCLR4 BHCS ROL
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
A BRSET5 BSET5 BPL DEC
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
B BRCLR5 BCLR5 BMI DBNZ
3 DIR 2 DIR 2 REL 3 DIR
5 4 3
C BRSET6 BSET6 BMC INC
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
D BRCLR6 BCLR6 BMS TST
3 DIR 2 DIR 2 REL 2 DIR
5 4 3
E BRSET7 BSET7 BIL
3 DIR 2 DIR 2 REL
5 4 3
F BRCLR7 BCLR7 BIH CLR
3 DIR 2 DIR 2 REL 2 DIR
INH Inherent REL Relative
IMM Immediate IX Indexed, No Offset
DIR Direct IX1 Indexed, 8-Bit Offset
EXT Extended IX2 Indexed, 16-Bit Offset
DD Direct-Direct IMD Immediate-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*
Pre-byte for stack pointer indexed instructions
Table 7-2. Opcode Map
Read-Modify-Write
INH INH IX1 SP1
4 5 6 9E6
4 1 1 4 5
NEGA NEGX NEG NEG
1 INH 1 INH 2 IX1 3 SP1
5 4 4 5 6
CBEQA CBEQX CBEQ CBEQ
3 IMM 3 IMM 3 IX1+ 4 SP1
5 7 3
MUL DIV NSA
1 INH 1 INH 1 INH
4 1 1 4 5
COMA COMX COM COM
1 INH 1 INH 2 IX1 3 SP1
4 1 1 4 5
LSRA LSRX LSR LSR
1 INH 1 INH 2 IX1 3 SP1
4 3 4 3
LDHX LDHX CPHX
3 IMM 2 DIR 3 IMM
4 1 1 4 5
RORA RORX ROR ROR
1 INH 1 INH 2 IX1 3 SP1
4 1 1 4 5
ASRA ASRX ASR ASR
1 INH 1 INH 2 IX1 3 SP1
4 1 1 4 5
LSLA LSLX LSL LSL
1 INH 1 INH 2 IX1 3 SP1
4 1 1 4 5
ROLA ROLX ROL ROL
1 INH 1 INH 2 IX1 3 SP1
4 1 1 4 5
DECA DECX DEC DEC
1 INH 1 INH 2 IX1 3 SP1
5 3 3 5 6
DBNZA DBNZX DBNZ DBNZ
2 INH 2 INH 3 IX1 4 SP1
4 1 1 4 5
INCA INCX INC INC
1 INH 1 INH 2 IX1 3 SP1
3 1 1 3 4
TSTA TSTX TST TST
1 INH 1 INH 2 IX1 3 SP1
5 4 4
MOV MOV MOV
3 DD 2 DIX+ 3 IMD
3 1 1 3 4
CLRA CLRX CLR CLR
1 INH 1 INH 2 IX1 3 SP1
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
Control
IX INH INH IMM DIR
7 8 9 A B
3 7 3 2
NEG RTI BGE SUB SUB
1 IX 1 INH 2 REL 2 IMM 2 DIR
4 4 3 2
CBEQ RTS BLT CMP CMP
2 IX+ 1 INH 2 REL 2 IMM 2 DIR
2 3 2
DAA BGT SBC SBC
1 INH 2 REL 2 IMM 2 DIR
3 9 3 2
COM SWI BLE CPX CPX
1 IX 1 INH 2 REL 2 IMM 2 DIR
3 2 2 2
LSR TAP TXS AND AND
1 IX 1 INH 1 INH 2 IMM 2 DIR
4 1 2 2
CPHX TPA TSX BIT BIT
2 DIR 1 INH 1 INH 2 IMM 2 DIR
3 2 2
ROR PULA LDA LDA
1 IX 1 INH 2 IMM 2 DIR
3 2 1 2
ASR PSHA TAX AIS STA
1 IX 1 INH 1 INH 2 IMM 2 DIR
3 2 1 2
LSL PULX CLC EOR EOR
1 IX 1 INH 1 INH 2 IMM 2 DIR
3 2 1 2
ROL PSHX SEC ADC ADC
1 IX 1 INH 1 INH 2 IMM 2 DIR
3 2 2 2
DEC PULH CLI ORA ORA
1 IX 1 INH 1 INH 2 IMM 2 DIR
4 2 2 2
DBNZ PSHH SEI ADD ADD
2 IX 1 INH 1 INH 2 IMM 2 DIR
3 1 1
INC CLRH RSP JMP
1 IX 1 INH 1 INH 2 DIR
2 1 4
TST NOP BSR JSR
1 IX 1 INH 2 REL 2 DIR
4 1 2
MOV STOP LDX LDX
*
2 IX+D 1 INH 2 IMM 2 DIR
2 1 1 2
CLR WAIT TXA AIX STX
1 IX 1 INH 1 INH 2 IMM 2 DIR
MSB
LSB
Low Byte of Opcode in Hexadecimal 0
Register/Memory
EXT IX2 SP2 IX1
C D 9ED E
3 4 4 5 3
SUB SUB SUB SUB
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
CMP CMP CMP CMP
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
SBC SBC SBC SBC
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
CPX CPX CPX CPX
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
AND AND AND AND
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
BIT BIT BIT BIT
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
LDA LDA LDA LDA
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
STA STA STA STA
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
EOR EOR EOR EOR
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
ADC ADC ADC ADC
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
ORA ORA ORA ORA
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
ADD ADD ADD ADD
3 EXT 3 IX2 4 SP2 2 IX1
2 3 4 3
JMP JMP JMP
3 EXT 3 IX2 2 IX1
4 5 6 5
JSR JSR JSR
3 EXT 3 IX2 2 IX1
3 4 4 5 3
LDX LDX LDX LDX
3 EXT 3 IX2 4 SP2 2 IX1
3 4 4 5 3
STX STX STX STX
3 EXT 3 IX2 4 SP2 2 IX1
0 High Byte of Opcode in Hexadecimal
5 Cycles
BRSET0 Opcode Mnemonic
3 DIR Number of Bytes / Addressing Mode
SP1 IX
9EE F
4 2
SUB SUB
3 SP1 1 IX
4 2
CMP CMP
3 SP1 1 IX
4 2
SBC SBC
3 SP1 1 IX
4 2
CPX CPX
3 SP1 1 IX
4 2
AND AND
3 SP1 1 IX
4 2
BIT BIT
3 SP1 1 IX
4 2
LDA LDA
3 SP1 1 IX
4 2
STA STA
3 SP1 1 IX
4 2
EOR EOR
3 SP1 1 IX
4 2
ADC ADC
3 SP1 1 IX
4 2
ORA ORA
3 SP1 1 IX
4 2
ADD ADD
3 SP1 1 IX
2
JMP
1 IX
4
JSR
1 IX
4 2
LDX LDX
3 SP1 1 IX
4 2
STX STX
3 SP1 1 IX