Event Counter - Freescale Semiconductor SC140 DSP Core Reference Manual

Digital signal processor (dsp) core
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EOnCE Module Internal Architecture
Register Name
PC_NEXT
PC_LAST
PC_DETECT
The functionality of the EOnCE controller registers is described in
Registers."

4.5.2 Event Counter

The 64-bit event counter is used to count one of the following possible events:
System clock
Instruction execution
Event detection by an event detection channel
Tracing into the trace buffer
Execution of the DEBUGEV instruction
Off-core events from the EC input signals
When the core is in debug state, the event counter does not count core clocks.
The event counter programming model includes three registers:
Event counter register (ECNT_CTRL)
Downcount event counter value register (ECNT_VAL)
Extension counter value register (ECNT_EXT)
4-18
Table 4-6. EOnCE Controller Register Set
Description
PC of the next execution set
PC of the last execution set
PC breakpoint address register
Section 4.7, "EOnCE Controller
SC140 DSP Core Reference Manual

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