Interrupts - Freescale Semiconductor MC68HC908MR16 Datasheet

Serial Peripheral Interface Module (SPI)

15.7 Interrupts

Four SPI status flags can be enabled to generate CPU interrupt requests as shown in
Flag
SPTE transmitter empty
SPRF receiver full
OVRF overflow
MODF mode fault
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU
interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt
requests, provided that the SPI is enabled (SPE = 1). (See
ERRIE
MODF
OVRF
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error
CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF
bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
These sources in the SPI status and control register can generate CPU interrupt requests:
• SPI receiver full bit (SPRF) — The SPRF bit becomes set every time a byte transfers from the shift
register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate either an SPI receiver/error or CPU interrupt.
• SPI transmitter empty (SPTE) — The SPTE bit becomes set every time a byte transfers from the
transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate either an SPTE or CPU interrupt request.
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Table 15-2. SPI Interrupts
SPI transmitter CPU interrupt request (SPTIE = 1, SPE = 1)
SPI receiver CPU interrupt request (SPRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
SPI receiver/error interrupt request (ERRIE = 1)
SPTE SPTIE
SPRIE SPRF
Figure 15-11. SPI Interrupt Request Generation
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Request
Figure 15-11.)
SPE
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Table 15-2.
Freescale Semiconductor