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User Manuals: ARM PL310 Cache Controller
Manuals and User Guides for ARM PL310 Cache Controller. We have
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ARM PL310 Cache Controller manual available for free PDF download: Technical Reference Manual
ARM PL310 Technical Reference Manual (60 pages)
PrimeCell Level 2 MBIST Controller
Brand:
ARM
| Category:
Controller
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
9
About this Manual
10
Key to Timing Diagram Conventions
12
Feedback
14
Chapter 1 Introduction
15
About the MBIST Controller
16
Cache Controller MBIST Configuration
16
Figure 1-2 MBIST Controller Wiring Diagram
17
MBIST Controller Interface
17
Figure 1-3 Traditional Method of Interfacing MBIST
18
Figure 1-4 Cache Controller MBIST Interface
19
Table 1-1 Cache Controller MBIST Interface Signals
19
Product Revisions
21
Chapter 2 Functional Description
23
Functional Overview
24
Figure 2-1 Cache Controller MBIST and RAM Interfaces
25
Table 2-1 Cache Controller Compiled RAM Latency
26
Table 2-2 MBISTADDR and MBISTDIN Mapping for Data RAM, 8-Way
27
Figure 2-2 Cache Controller Compiled RAM Latency
27
Table 2-3 MBISTADDR and MBISTDIN Mapping for Data RAM, 16-Way
28
Figure
28
Table 2-4 Writes for Data RAM Testing
29
Figure 2-3 Cache Controller MBIST Paths for Data RAM Testing
29
Table 2-5 MBISTADDR and MBISTDIN Mapping for Tag RAM, 8-Way
30
Table 2-6 MBISTADDR and MBISTDIN Mapping for Tag RAM, 16-Way
30
Figure 2-4 Cache Controller MBIST Paths for Tag RAM Testing
31
Table 2-7 MBISTTX Signals
32
Figure 2-5 MBIST Controller Block
32
Table 2-8 MBISTRX Signals
33
Table 2-9 MBIST Controller Top Level I/O
33
Functional Operation
35
Figure 2-6 Loading the MBIST Controller Instruction
35
Figure 2-7 Starting the MBIST Test
36
Figure 2-8 Detecting an MBIST Failure
36
Table 2-10 Data Log Format
37
Figure 2-9 Start of Data Log Retrieval
37
Figure 2-10 End of Data Log Retrieval
37
Figure 2-11 Start of Bitmap Data Log Retrieval
38
Figure 2-12 End of Bitmap Data Log Retrieval
38
Chapter 3 MBIST Instruction Register
39
About the MBIST Instruction Register
39
Field Descriptions
39
Figure
39
Field Descriptions
42
Table 3-1 Pattern Field Encoding
42
Table 3-2 Go/No-Go Test Pattern
44
Control Field, MBIR[54:49]
45
Read Latency and Write Latency Fields, MBIR[44:41] and MBIR[48:45]
45
Table 3-3 Control Field Encoding
45
Table 3-4 Read Latency Field Encoding
46
Table 3-5 Write Latency Field Encoding
46
Y-Address and X-Address Fields, MBIR[36:33] and MBIR[40:37]
47
Figure 3-2 Example Data RAM Topology
48
Figure 3-3 MBIST Address Scrambling
49
Table 3-6 Y-Address Field Encoding
50
Table 3-7 X-Address Field Encoding
50
Table 3-8 Required Sums of X-Address and Y-Address Fields for Data RAM
51
Data Seed Field, MBIR[32:29]
52
Table 3-9 Required Sums of X-Address and Y-Address Fields for Tag RAM
52
Enables Field, MBIR[28:11]
53
Table 3-10 Enables Field Encoding
53
Cache Size Field, MBIR[8:6]
54
Column Width Field, MBIR[10:9]
54
Table 3-11 Column Width Field Encoding
54
Table 3-12 Cache Size Field Encoding
54
Lockdown by Line Support Field, MBIR[1]
55
Parity Support Field, MBIR[2]
55
Table 3-13 Way Size Field Encoding
55
Way Configuration Field, MBIR[0]
55
Way Size Field, MBIR[5:3]
55
Table A-1 MBIST Controller Interface Signals
58
Table A-2 Miscellaneous Signals
60
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