Standby Function Control Register - NEC mPD780852 Series Preliminary User's Manual

20.1.2 Standby function control register

The wait time after the STOP mode is cleared upon interrupt request is controlled with the oscillation stabilization
time select register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H.
Figure 20-1. Oscillation Stabilization Time Select Register (OSTS) Format
Address: FFFAH After Reset: 04H R/W
Symbol 7
OSTS 0
OSTS2
0
0
0
0
1
Other than above
Caution The wait time after the STOP mode is cleared does not include the time (see "a" in the illustration
below) from STOP mode clear to clock oscillation start, regardless of clearance by RESET input
or by interrupt request generation.
Remarks 1. f : Main system clock oscillation frequency
X
2. Figures in parentheses apply to operation with f
264
CHAPTER 20 STANDBY FUNCTION
6 5 4
0 0 0
OSTS1 OSTS0 Oscillation Stabilization Time Selection When STOP Mode Is Cleared
12
0 0 2 /f
X
14
0 1 2 /f
X
15
1 0 2 /f
X
16
1 1 2 /f
X
17
0 0 2 /f
X
Setting prohibited
STOP mode clear
X1 pin voltage
waveform
a
V
SS
Preliminary User's Manual U14581EJ3V0UM00
3 2
0 OSTS2
(488 µ s)
(1.95 ms)
(3.91 ms)
(7.81 ms)
(15.6 ms)
= 8.38 MHz.
X
1 0
OSTS1 OSTS0