HP 98568A Installation Instruction page 113

HP 98622A GPIO Interface
Table 5-3.
Interrupt Switch Switch
Level 1
0
3 0 0
4 0 1
5 1 0
6 1 1
b. Set the Data-in Clock Source switches (labeled U2). If connecting an HP
9884A Paper Tape Punch to this interface, set these switches as shown in
Figure 5-6.
The right-hand 3 switches set the clock source for the data input lines
DIO through DI7. The left-hand 3 switches set the clock source for the
data input lines DI8 through D115. Select only one clock source (logic 0)
for each group of input lines. The three clock sources are:
• RD. This mode causes the data to be clocked into the input register
when the register is read. It accomplishes this by clocking the leading
edge of the output enable signal of the register.
• BSY. This mode clocks the data into the data input register by a
ready-to-busy transition of the PFLG line. This transition also clears
the PCTL line.
• RDY. This mode clocks the data into the data input register by a
busy-to-ready transition of the PFLG line.
c. Set the Option Select switches (labeled U 1) by referring to Table 5-4. If
connecting an HP 9884A Paper Tape punch to this interface, set all of
these switches to 1.
Adding Interface Cards 5-17