Receive Interrupt Mask Clear Register (Rxintmaskclear); Receive Interrupt Mask Clear Register (Rxintmaskclear) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in
Table 55.
Figure 56. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
31
15
7 6
RX7MASK RX6MASK
R/W1C-0 R/W1C-0
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 55. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
Bit Field Value
31-8 Reserved 0
7 RX7MASK 0-1
6 RX6MASK 0-1
5 RX5MASK 0-1
4 RX4MASK 0-1
3 RX3MASK 0-1
2 RX2MASK 0-1
1 RX1MASK 0-1
0 RX0MASK 0-1
SPRUEQ6 – December 2007
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Reserved
Reserved
5 4
RX5MASK RX4MASK
R/W1C-0 R/W1C-0
Description
Reserved
Receive channel 7 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Receive channel 6 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Receive channel 5 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Receive channel 4 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Receive channel 3 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Receive channel 2 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Receive channel 1 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Receive channel 0 mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
R-0
R-0
3 2
RX3MASK RX2MASK
R/W1C-0 R/W1C-0
Figure 56 and described in
16
8
1 0
RX1MASK RX0MASK
R/W1C-0 R/W1C-0
99