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Architecture
If the rate of transmit pulse interrupt inputs is much less than the target transmit pulse interrupt rate
specified in CMTXINTMAX, then the interrupts are not blocked to the CPU. If the transmit pulse interrupt
rate is greater than the specified target rate in CMTXINTMAX, the interrupt is paced at the rate specified
in this register, which should be written with a value between 2 and 63 inclusive, indicating the target
number of interrupts per 1 ms going to the CPU. Similarly, the number of receive interrupt pulses to the
CPU is also separately controlled.
2.7
MDIO Module
The MDIO module is used to manage up to 32 physical layer (PHY) devices connected to the Ethernet
Media Access Controller (EMAC). The DM646x device supports a single PHY being connected to the
EMAC at any given time. The MDIO module is designed to allow almost transparent operation of the
MDIO interface with little maintenance from the CPU.
The MDIO module continuously polls 32 MDIO addresses in order to enumerate all PHY devices in the
system. Once a PHY device has been detected, the MDIO module reads the MDIO PHY link status
register (LINK) to monitor the PHY link state. Link change events are stored in the MDIO module, which
can interrupt the CPU. This storing of the events allows the CPU to poll the link status of the PHY device
without continuously performing MDIO module accesses. However, when the CPU must access the MDIO
module for configuration and negotiation, the MDIO module performs the MDIO read or write operation
independent of the CPU. This independent operation allows the processor to poll for completion or
interrupt the CPU once the operation has completed.
2.7.1
MDIO Module Components
The MDIO module
MDIO), and to the CPU through the EMAC control module and the configuration bus. The MDIO module
consists of the following logical components:
MDIO clock generator
Global PHY detection and link state monitoring
Active PHY monitoring
PHY register user access
EMAC
control
module
2.7.1.1
MDIO Clock Generator
The MDIO clock generator controls the MDIO clock based on a divide-down of the peripheral clock
(PLL1/6) in the EMAC control module. The MDIO clock is specified to run up to 2.5 MHZ, although typical
operation would be 1.0 MHZ. Since the peripheral clock frequency is variable (PLL1/6), the application
software or driver controls the divide-down amount.
34
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
(Figure
10) interfaces to the PHY components through two MDIO pins (MDCLK and
Figure 10. MDIO Module Block Diagram
Peripheral
clock
generator
USERINT
LINKINT
monitoring
Control
registers
Configuration bus
and logic
MDIO
clock
MDIO
interface
PHY
PHY
polling
www.ti.com
MDCLK
MDIO
SPRUEQ6 – December 2007
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