Mac Interrupt Status (Unmasked) Register (Macintstatraw); Mac Interrupt Status (Masked) Register (Macintstatmasked); Mac Interrupt Status (Unmasked) Register (Macintstatraw) Field Descriptions; Mac Interrupt Status (Masked) Register (Macintstatmasked) Field Descriptions - Texas Instruments TMS320DM646x User Manual

Ethernet Media Access Controller (EMAC) Registers

5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)

The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in
described in Table
Figure 57. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
31
15
LEGEND: R = Read only; -n = value after reset
Table 56. MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
Bit Field
31-2 Reserved
1 HOSTPEND
0 STATPEND

5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)

The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in
described in Table
Figure 58. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
31
15
LEGEND: R = Read only; -n = value after reset
Table 57. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
Bit Field
31-2 Reserved
1 HOSTPEND
0 STATPEND
100 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
56.
Reserved
R-0
Value Description
0 Reserved
0-1 Host pending interrupt (HOSTPEND); raw interrupt read (before mask)
0-1 Statistics pending interrupt (STATPEND); raw interrupt read (before mask)
57.
Reserved
R-0
Value Description
0 Reserved
0-1 Host pending interrupt (HOSTPEND); masked interrupt read
0-1 Statistics pending interrupt (STATPEND); masked interrupt read
Reserved
R-0
Reserved
R-0
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Figure 57 and
16
2 1 0
HOSTPEND STATPEND
R-0 R-0
Figure 58 and
16
2 1 0
HOSTPEND STATPEND
R-0 R-0
SPRUEQ6 – December 2007
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