Texas Instruments TMS320DM646x User Manual page 9

48 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
49 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
50 MAC Input Vector Register (MACINVECTOR) Field Descriptions
51 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
52 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
53 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
54 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
55 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
56 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
57 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
58 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
59 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
60 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions
61 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
62 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
63 Receive Maximum Length Register (RXMAXLEN) Field Descriptions
64 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
65 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
66 Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) Field Descriptions
67 Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions
68 MAC Control Register (MACCONTROL) Field Descriptions
69 MAC Status Register (MACSTATUS) Field Descriptions
70 Emulation Control Register (EMCONTROL) Field Descriptions
71 FIFO Control Register (FIFOCONTROL) Field Descriptions
72 MAC Configuration Register (MACCONFIG) Field Descriptions
73 Soft Reset Register (SOFTRESET) Field Descriptions
74 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
75 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
76 MAC Hash Address Register 1 (MACHASH1) Field Descriptions
77 MAC Hash Address Register 2 (MACHASH2) Field Descriptions
78 Back Off Test Register (BOFFTEST) Field Descriptions
79 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
80 Receive Pause Timer Register (RXPAUSE) Field Descriptions
81 Transmit Pause Timer Register (TXPAUSE) Field Descriptions
82 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
83 MAC Address High Bytes Register (MACADDRHI) Field Descriptions
84 MAC Index Register (MACINDEX) Field Descriptions
85 Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) Field Descriptions
86 Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) Field Descriptions
87 Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
88 Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
A-1 Physical Layer Definitions
SPRUEQ6 - December 2007
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List of Tables 9