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Summary of Contents for Texas Instruments TMS320DM646x
- Page 1 TMS320DM646x DMSoC DDR2 Memory Controller User's Guide Literature Number: SPRUEQ4C February 2009...
- Page 2 SPRUEQ4C – February 2009 Submit Documentation Feedback...
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Page 3: Table Of Contents
Contents ............................Preface ......................... Introduction ....................Purpose of the Peripheral ........................Features ....................Functional Block Diagram ..................Supported Use Case Statement ................Industry Standard(s) Compliance Statement ........................Architecture ......................Clock Control ......................Memory Map ...................... Signal Descriptions ....................Protocol Description(s) ................... -
Page 4: List Of Figures
www.ti.com List of Figures .................. Data Paths to DDR2 Memory Controller ................. DDR2 Memory Controller Clock Block Diagram ..................DDR2 Memory Controller Signals ......................Refresh Command ......................DCAB Command ......................DEAC Command ......................ACTV Command ....................DDR2 READ Command ....................DDR2 WRT Command .................. - Page 5 www.ti.com List of Tables ......................PLLC2 Configuration ................. DDR2 Memory Controller Signal Descriptions ....................DDR2 SDRAM Commands ................Truth Table for DDR2 SDRAM Commands .................... Addressable Memory Ranges ............Bank Configuration Register Fields for Address Mapping ..........Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM ..........
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Page 6: Preface
Preface SPRUEQ4C – February 2009 Read This First About This Manual This document describes the DDR2 memory controller in the TMS320DM646x Digital Media System-on-Chip (DMSoC). Notational Conventions This document uses the following conventions. • Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h. -
Page 7: Introduction
SPRUEQ4C – February 2009 DDR2 Memory Controller Introduction This document describes the DDR2 memory controller in the TMS320DM646x Digital Media System-on-Chip (DMSoC). Purpose of the Peripheral The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAM devices. -
Page 8: Supported Use Case Statement
Architecture www.ti.com Figure 1. Data Paths to DDR2 Memory Controller DDR2 Master External memory peripherals DDR2 SDRAM controller EDMA VPSS Supported Use Case Statement The DDR2 memory controller supports JESD79D-2A DDR2-667 SDRAM memories utilizing either 32-bit or 16-bit of the DDR2 memory controller data bus. See Section 3 for more details. -
Page 9: Ddr2 Memory Controller Clock Block Diagram
PLL multiplier and divider settings to achieve certain DDR2 frequencies. The data in Table 1 is derived by assuming a 27-MHZ reference clock. See the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9) for information on the PLL controller. -
Page 10: Memory Map
Architecture www.ti.com 2.1.3 DR2 Memory Controller Internal Clock Domains There are two clock domains within the DDR2 memory controller. The two clock domains are driven by VCLK and a divided-down by 2 version of PLL2_SYSCLK1 called MCLK. The command FIFO, write FIFO, and read FIFO described in Section 2.7 are all on the VCLK domain. -
Page 11: Protocol Description(S)
Architecture www.ti.com Table 2. DDR2 Memory Controller Signal Descriptions Type Description DDR_CLK Clock: Clock output. DDR_CLK Clock: Differential clock output. DDR_CKE Clock enable: Active high. DDR_CS Chip select: Active low. DDR_WE Write enable: Active low, command output. DDR_RAS Row access strobe: Active low, command output. DDR_CAS Column access strobe: Active low, command output. -
Page 12: Truth Table For Ddr2 Sdram Commands
Architecture www.ti.com Table 4. Truth Table for DDR2 SDRAM Commands DDR2 SDRAM: BA[2:0] A[14:11, 9:0] DDR2 memory controller: DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_BA[2:0] DDR_A[14:11, 9:0] DDR_A[10] Previous Cycles Current Cycle ACTV Bank Row Address DCAB DEAC Bank OP Code EMRS OP Code READ... -
Page 13: Refresh Command
Architecture www.ti.com 2.4.1 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM memory (Figure 4). REFR is automatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banks selected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate (RR) bit in the SDRAM refresh control register (SDRCR). -
Page 14: Dcab Command
Architecture www.ti.com 2.4.2 Deactivation (DCAB and DEAC) The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller or following the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) and mode set register commands (MRS and EMRS). -
Page 15: Deac Command
Architecture www.ti.com The DEAC command closes a single bank of memory specified by the bank select signals. Figure 6 shows the timings diagram for a DEAC command. Figure 6. DEAC Command DEAC DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_RAS DDR_CAS DDR_WE DDR_A[14:11, 9:0] DDR_A[10] DDR_BA[2:0] Bank... -
Page 16: Actv Command
Architecture www.ti.com 2.4.3 Activation (ACTV) The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects the row. -
Page 17: Ddr2 Read Command
Architecture www.ti.com 2.4.4 READ Command Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READ command initiates a burst read operation to an active row. During the READ command, DDR_CAS drives low, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bank address is driven on DDR_BA[2:0]. -
Page 18: Ddr2 Wrt Command
Architecture www.ti.com 2.4.5 Write (WRT) Command Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following the WRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes have a burst length of 8. -
Page 19: Memory Width And Byte Alignment
Architecture www.ti.com 2.4.6 Mode Register Set (MRS and EMRS) DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation. These registers control burst type, burst length, CAS latency, DLL enable/disable (on DDR2 device), single-ended strobe, etc. The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands. -
Page 20: Address Mapping
Architecture www.ti.com Figure 11. Byte Alignment DDR2 memory controller data bus DDR_D[31:24] DDR_D[23:16] DDR_D[15:8] DDR_D[7:0] 32-bit memory device 16-bit memory device Address Mapping The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. This statement is true regardless of the number of external physical devices mapped to a given chip select space. -
Page 21: Logical Address-To-Ddr2 Sdram Address Map For 32-Bit Sdram
Architecture www.ti.com By traversing across banks while remaining on the same row/page, the DDR2 memory controller maximizes the number of activated banks for a linear access. This results in the maximum number of open pages when performing a linear access being equal to the number of banks. Note that the DDR2 memory controller never opens more than one page per bank. -
Page 22: Logical Address-To-Ddr2 Sdram Address Map
Architecture www.ti.com Figure 12. Logical Address-to-DDR2 SDRAM Address Map Col. 0 Col. 1 Col. 2 Col. 3 Col. 4 Col. M−1 Col. M Row 0, bank 0 Row 0, bank 1 Row 0, bank 2 Row 0, bank P Row 1, bank 0 Row 1, bank 1 Row 1, bank 2 Row 1, bank P... -
Page 23: Ddr2 Memory Controller Interface
Architecture www.ti.com Figure 13. DDR2 SDRAM Column, Row, and Bank Access Bank 0 0 1 2 3 Row 0 Row 1 Bank 1 Row 2 Row 0 Row 1 Bank 2 Row 2 Row 0 Row 1 Bank P 0 1 2 3 Row 2 Row 0 Row 1... -
Page 24: Ddr2 Memory Controller Fifo Block Diagram
Architecture www.ti.com Figure 14. DDR2 Memory Controller FIFO Block Diagram Command/Data Command Command FIFO Scheduler to Memory Write FIFO Write Data to Memory Read FIFO Read Data from Memory Registers Command Data 2.7.1 Command Ordering and Scheduling, Advanced Concept The DDR2 memory controller performs command re-ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput. - Page 25 Architecture www.ti.com Besides commands received from on-chip resources, the DDR2 memory controller also issues refresh commands. The DDR2 memory controller attempts to delay refresh commands as long as possible to maximize performance while meeting the SDRAM refresh requirements. As the DDR2 memory controller issues read, write, and refresh commands to DDR2 SDRAM memory, it adheres to the following rules: 1.
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Page 26: Refresh Scheduling
Architecture www.ti.com Refresh Scheduling The DDR2 memory controller issues autorefresh (REFR) commands to DDR2 SDRAM devices at a rate defined in the refresh rate (RR) bit field in the SDRAM refresh control register (SDRCR). A refresh interval counter is loaded with the value of the RR bit field and decrements by 1 each cycle until it reaches zero. Once the interval counter reaches zero, it reloads with the value of the RR bit. -
Page 27: 2.10 Reset Considerations
The Power and Sleep Controller (PSC) acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). -
Page 28: 2.11 Vtp Io Buffer Calibration
Architecture www.ti.com 2.11 VTP IO Buffer Calibration The DDR2 memory controller is able to control the impedance of the output IO. This feature allows the DDR2 memory controller to tune the output impedance of the IO to match that of the PCB board. Control of the output impedance of the IO is an important feature because impedance matching reduces reflections, creating a cleaner board design. -
Page 29: Ddr2 Sdram Configuration By Mrs Command
Architecture www.ti.com Table 12. DDR2 SDRAM Configuration by MRS Command DDR2 Memory Controller DDR2 SDRAM Address Bus Value Register Bit DDR2 SDRAM Field Function Selection DDR_A[12] Power Down Exit Fast exit DDR_A[11:9] t_WR 11:9 Write Recovery Write recovery from autoprecharge. Value of 2, 3, 4, 5, or 6 is programmed based on value of the T_WR bit in the SDRAM timing register (SDTIMR). -
Page 30: 2.13 Interrupt Support
Architecture www.ti.com 2.12.2 Initializing Following Device Power Up and Device RESET CAUTION The following power up sequence is preliminary and is documented to reflect the intended-use case. This power-up sequence may change at a future date. Following device power up, the DDR2 memory controller is held in reset with the internal clocks to the module gated off. -
Page 31: 2.14 Dma Event Support
Figure 16 shows the connections between the DDR2 memory controller, PSC, and PLLC2. For detailed information on power management procedures using the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). Before gating clocks off, the DDR2 memory controller must place the DDR2 SDRAM memory in self-refresh mode by setting the SR_PD bit in the SDRAM refresh control register (SDRCR) to 1. -
Page 32: 2.16 Emulation Considerations
MCLK is running and the DLL is powered up. 7. Perform a soft reset to the DDR2 memory controller via the PSC. For details on programming the PSC, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (SPRUEP9). 2.16 Emulation Considerations The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory. -
Page 33: Use Cases
Use Cases www.ti.com Use Cases The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses. The programmability inherent to the DDR2 memory controller provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices. By programming the SDRAM bank configuration register (SDBCR), SDRAM refresh control register (SDRCR), SDRAM timing register (SDTIMR), and SDRAM timing register 2 (SDTIMR2), the DDR2 memory controller can be configured to meet the data sheet specification for JESD79D-2A compliant DDR2 SDRAM. -
Page 34: Connecting Ddr2 Memory Controller For 32-Bit Connection
Use Cases www.ti.com Figure 17. Connecting DDR2 Memory Controller for 32-Bit Connection DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR2 DDR_RAS memory DDR_CAS controller DDR2 LDQM DDR_DQM0 memory x16-bit DDR_DQM1 UDQM DDR_DQS0 LDQS DDR_DQS0 LDQS DDR_DQS1 UDQS DDR_DQS1 UDQS DDR_BA[2:0] BA[2:0] DDR_A[14:0] A[14:0] DDR_D[15:0] DQ[15:0]... -
Page 35: Connecting Ddr2 Memory Controller For 16-Bit Connection
Use Cases www.ti.com Figure 18. Connecting DDR2 Memory Controller for 16-Bit Connection DDR_CLK DDR_CLK DDR_CKE DDR2 DDR_CS memory DDR2 DDR_WE x16−bit memory DDR_RAS controller DDR_CAS DDR_DQM0 LDQM DDR_DQM1 UDQM DDR_DQS0 LDQS DDR_DQS0 LDQS DDR_DQS1 UDQS DDR_DQS1 UDQS DDR_BA[2:0] BA[2:0] DDR_A[14:0] A[14:0] DDR_D[15:0] DQ[15:0]... -
Page 36: Ddr2 Memory Refresh Specification
Use Cases www.ti.com 3.2.2 Configuring SDRAM Refresh Control Register (SDRCR) The SDRAM refresh control register (SDRCR) configures the DDR2 memory controller to meet the refresh requirements of the attached DDR2 device. SDRCR also allows the DDR2 memory controller to enter and exit self refresh and enable and disable the MCLK stopping. -
Page 37: Sdtimr Configuration
Use Cases www.ti.com 3.2.3 Configuring SDRAM Timing Registers (SDTIMR and SDTIMR2) The SDRAM timing register (SDTIMR) and SDRAM timing register 2 (SDTIMR2) configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device. Each field in SDTIMR and SDTIMR2 corresponds to a timing parameter in the DDR2 data sheet specification. -
Page 38: Ddrphycr Configuration
Use Cases www.ti.com 3.2.4 Configuring DDR PHY Control Register (DDRPHYCR) The DDR PHY control register (DDRPHYCR) contains a read latency (READLAT) field that helps the DDR2 memory controller determine when to sample read data. The READLAT field should be programmed to a value equal to CAS latency plus round trip board delay minus 1 (see Table 19). -
Page 39: Registers
Registers www.ti.com Registers Table 20 lists the memory-mapped registers for the DDR2 memory controller. See the device-specific data manual for the memory address of these registers. Table 20. DDR2 Memory Controller Registers Offset Acronym Register Description Section SDRSTAT SDRAM Status Register Section 4.1 SDBCR SDRAM Bank Configuration Register... -
Page 40: Sdram Bank Configuration Register (Sdbcr)
Registers www.ti.com SDRAM Bank Configuration Register (SDBCR) The SDRAM bank configuration register (SDBCR) contains fields that program the DDR2 memory controller to meet the specification of the attached DDR2 memory. These fields configure the DDR2 memory controller to match the data bus width, CAS latency, number of internal banks, and page size of the attached DDR2 memory. - Page 41 Registers www.ti.com Table 22. SDRAM Bank Configuration Register (SDBCR) Field Descriptions (continued) Field Value Description DDR2_TERM[0] 0-3h DDR2 termination resistor value. This bit is used in conjunction with the DDR2_TERM[1] bit to make a 2-bit field. This bit is writeable only when the BOOTUNLOCK bit is unlocked. To change this bit value, use the following sequence: 1.
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Page 42: Sdram Refresh Control Register (Sdrcr)
Registers www.ti.com Table 22. SDRAM Bank Configuration Register (SDBCR) Field Descriptions (continued) Field Value Description PAGESIZE 0-7h DDR2 page size. Defines the page size of each page of the external DDR2 memory. 256-word page requiring 8 column address bits. 512-word page requiring 9 column address bits. 1024-word page requiring 10 column address bits. -
Page 43: Sdram Timing Register (Sdtimr)
Registers www.ti.com SDRAM Timing Register (SDTIMR) The SDRAM timing register (SDTIMR) configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory. The SDTIMR is programmable only when the TIMUNLOCK bit in the SDRAM bank configuration register (SDBCR) is set to 1. Note that DDR_CLK is equal to the period of the DDR_CLK signal. -
Page 44: Sdram Timing Register 2 (Sdtimr2)
Registers www.ti.com SDRAM Timing Register 2 (SDTIMR2) Like the SDRAM timing register (SDTIMR), the SDRAM timing register 2 (SDTIMR2) also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory. The SDTIMR2 is programmable only when the TIMUNLOCK bit in the SDRAM bank configuration register (SDBCR) is set to 1. -
Page 45: Peripheral Bus Burst Priority Register (Pbbpr)
Registers www.ti.com Peripheral Bus Burst Priority Register (PBBPR) The peripheral bus burst priority register (PBBPR) helps prevent command starvation within the DDR2 memory controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made. The PR_OLD_COUNT bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command. -
Page 46: Interrupt Raw Register (Irr)
Registers www.ti.com Interrupt Raw Register (IRR) The interrupt raw register (IRR) displays the raw status of the interrupt. If the interrupt condition occurs, the corresponding bit in IRR is set independent of whether or not the interrupt is enabled. The IRR is shown in Figure 25 and described in... -
Page 47: Interrupt Masked Register (Imr)
Registers www.ti.com Interrupt Masked Register (IMR) The interrupt masked register (IMR) displays the status of the interrupt when it is enabled. If the interrupt condition occurs and the corresponding bit in the interrupt mask set register (IMSR) is set, then the IMR bit is set. -
Page 48: Interrupt Mask Set Register (Imsr)
Registers www.ti.com Interrupt Mask Set Register (IMSR) The interrupt mask set register (IMSR) enables the DDR2 memory controller interrupt. The IMSR is shown Figure 27 and described in Table Note: If the LTMSET bit in IMSR is set concurrently with the LTMCLR bit in the interrupt mask clear register (IMCR), the interrupt is not enabled and neither bit is set to 1. -
Page 49: Interrupt Mask Clear Register (Imcr)
Registers www.ti.com 4.10 Interrupt Mask Clear Register (IMCR) The interrupt mask clear register (IMCR) disables the DDR2 memory controller interrupt. Once an interrupt is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in Figure 28 described in Table... -
Page 50: Ddr Phy Control Register (Ddrphycr)
Registers www.ti.com 4.11 DDR PHY Control Register (DDRPHYCR) The DDR PHY control register (DDRPHYCR) configures the DDR2 memory controller DLL for operation and determines whether the DLL is in reset, whether it is powered up, and the read latency. The DDRPHYCR is shown in Figure 29 and described in... -
Page 51: Ddr Vtp Io Control Register (Vtpiocr)
Registers www.ti.com Table 31. DDR PHY Control Register (DDRPHYCR) Field Descriptions (continued) Field Value Description DDLL_MODE DDLL configuration. This bit must be cleared to 0. 72 degrees delay 90 degrees delay READLAT 0-Fh Read latency. Read latency is equal to CAS latency plus round trip board delay for data minus 1. -
Page 52: Appendix A Revision History
Appendix A www.ti.com Appendix A Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Table 31 Changed Description of IORX_TERM bit. Changed Description of INT_VREFEN bit. Changed Description of EXT_STRBEN bit. Changed Description of DDLL_MODE bit. - Page 53 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.