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Ethernet Media Access Controller (EMAC) Registers
5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in
Table
49.
Figure 50. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
31
15
7
6
TX7MASK
TX6MASK
R/W1C-0
R/W1C-0
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 49. Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7
TX7MASK
0-1
6
TX6MASK
0-1
5
TX5MASK
0-1
4
TX4MASK
0-1
3
TX3MASK
0-1
2
TX2MASK
0-1
1
TX1MASK
0-1
0
TX0MASK
0-1
94
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Reserved
Reserved
5
4
TX5MASK
TX4MASK
R/W1C-0
R/W1C-0
Description
Reserved
Transmit channel 7 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Transmit channel 6 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Transmit channel 5 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Transmit channel 4 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Transmit channel 3 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Transmit channel 2 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect.
R-0
R-0
3
2
TX3MASK
TX2MASK
R/W1C-0
R/W1C-0
www.ti.com
Figure 50
and described in
16
8
1
0
TX1MASK
TX0MASK
R/W1C-0
R/W1C-0
SPRUEQ6 – December 2007
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