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Ethernet Media Access Controller (EMAC) Registers
5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in
described in
Table
Figure 53. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
31
15
7
6
RX7PEND
RX6PEND
R-0
R-0
LEGEND: R = Read only; -n = value after reset
Table 52. Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7
RX7PEND
0-1
6
RX6PEND
0-1
5
RX5PEND
0-1
4
RX4PEND
0-1
3
RX3PEND
0-1
2
RX2PEND
0-1
1
RX1PEND
0-1
0
RX0PEND
0-1
96
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
52.
5
4
RX5PEND
RX4PEND
R-0
R-0
Description
Reserved
RX7PEND raw interrupt read (before mask)
RX6PEND raw interrupt read (before mask)
RX5PEND raw interrupt read (before mask)
RX4PEND raw interrupt read (before mask)
RX3PEND raw interrupt read (before mask)
RX2PEND raw interrupt read (before mask)
RX1PEND raw interrupt read (before mask)
RX0PEND raw interrupt read (before mask)
Reserved
R-0
Reserved
R-0
3
2
RX3PEND
RX2PEND
R-0
R-0
www.ti.com
Figure 53
and
16
8
1
0
RX1PEND
RX0PEND
R-0
R-0
SPRUEQ6 – December 2007
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