Transmit Channel 0-7 Completion Pointer Register (Txncp); Receive Channel 0-7 Completion Pointer Register (Rxncp); Transmit Channel N Completion Pointer Register (Txncp); Receive Channel N Completion Pointer Register (Rxncp) - Texas Instruments TMS320DM646x User Manual

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5.48 Transmit Channel 0-7 Completion Pointer Register (TXnCP)

The transmit channel 0-7 completion pointer register (TXnCP) is shown in
Table 87.
Figure 88. Transmit Channel n Completion Pointer Register (TXnCP)
31
15
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 87. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
Bit Field Value
31-0 TXnCP 0-FFFF FFFFh

5.49 Receive Channel 0-7 Completion Pointer Register (RXnCP)

The receive channel 0-7 completion pointer register (RXnCP) is shown in
Table 88.
Figure 89. Receive Channel n Completion Pointer Register (RXnCP)
31
15
LEGEND: R/W = Read/Write; -n = value after reset; -x = value is indeterminate after reset
Table 88. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
Bit Field Value
31-0 RXnCP 0-FFFF FFFFh
SPRUEQ6 – December 2007
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TXnCP
R/W-x
TXnCP
R/W-x
Description
Transmit channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
RXnCP
R/W-x
RXnCP
R/W-x
Description
Receive channel n completion pointer register is written by the host with the buffer descriptor
address for the last buffer processed by the host during interrupt processing. The EMAC uses the
value written to determine if the interrupt should be deasserted.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Ethernet Media Access Controller (EMAC) Registers
Figure 88
Figure 89
and described in
16
0
and described in
16
0
123