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Ethernet Media Access Controller (EMAC) Registers
5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)
The receive interrupt mask set register (RXINTMASKSET) is shown in
Table
54.
31
15
7
6
RX7MASK
RX6MASK
R/W1S-0
R/W1S-0
LEGEND: R = Read only; R/W = Read/Write; W1S = Write 1 to set, write of 0 has no effect; -n = value after reset
Table 54. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
Bit
Field
Value
31-8
Reserved
0
7
RX7MASK
0-1
6
RX6MASK
0-1
5
RX5MASK
0-1
4
RX4MASK
0-1
3
RX3MASK
0-1
2
RX2MASK
0-1
1
RX1MASK
0-1
0
RX0MASK
0-1
98
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Figure 55. Receive Interrupt Mask Set Register (RXINTMASKSET)
5
4
RX5MASK
RX4MASK
R/W1S-0
R/W1S-0
Description
Reserved
Receive channel 7 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Receive channel 6 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Receive channel 5 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Receive channel 4 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Receive channel 3 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Receive channel 2 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Receive channel 1 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Receive channel 0 mask set bit. Write 1 to enable interrupt, a write of 0 has no effect.
Reserved
R-0
Reserved
R-0
3
2
RX3MASK
RX2MASK
R/W1S-0
R/W1S-0
www.ti.com
Figure 55
and described in
1
RX1MASK
RX0MASK
R/W1S-0
R/W1S-0
SPRUEQ6 – December 2007
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