Transmit Interrupt Status (Masked) Register (Txintstatmasked); Transmit Interrupt Status (Masked) Register (Txintstatmasked) Field Descriptions - Texas Instruments TMS320DM646x User Manual

Ethernet Media Access Controller (EMAC) Registers
5.8

Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)

The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in
described in Table
Figure 48. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
31
15
7 6
TX7PEND TX6PEND
R-0 R-0
LEGEND: R = Read only; -n = value after reset
Table 47. Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
Bit Field Value
31-8 Reserved 0
7 TX7PEND 0-1
6 TX6PEND 0-1
5 TX5PEND 0-1
4 TX4PEND 0-1
3 TX3PEND 0-1
2 TX2PEND 0-1
1 TX1PEND 0-1
0 TX0PEND 0-1
92 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
47.
5 4
TX5PEND TX4PEND
R-0 R-0
Description
Reserved
TX7PEND masked interrupt read
TX6PEND masked interrupt read
TX5PEND masked interrupt read
TX4PEND masked interrupt read
TX3PEND masked interrupt read
TX2PEND masked interrupt read
TX1PEND masked interrupt read
TX0PEND masked interrupt read
Reserved
R-0
Reserved
R-0
3 2
TX3PEND TX2PEND
R-0 R-0
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Figure 48 and
16
8
1 0
TX1PEND TX0PEND
R-0 R-0
SPRUEQ6 – December 2007
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