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3.7
EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
The transmit interrupt enable register (CMTXINTEN) is shown in
Figure 19. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN)
Bit
Field
31-8
Reserved
7-0
TXPULSEEN[n]
SPRUEQ6 – December 2007
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R-0
Field Descriptions
Value
Description
0
Reserved
Transmit interrupt (TXPENDn) enable. Each bit controls the corresponding channel n transmit
interrupt.
Bit n = 0,channel n transmit interrupt (TXPENDn) is disabled.
Bit n = 1, channel n transmit interrupt (TXPENDn) is enabled.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Figure 19
Reserved
R-0
8
7
EMAC Control Module Registers
and described in
Table
TXPULSEEN
R/W-0
16.
16
0
65