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Ethernet Media Access Controller (EMAC) Registers
5.29 MAC Control Register (MACCONTROL)
The MAC control register (MACCONTROL) is shown in
31
15
14
Reserved
RXOFFLENBLOCK
R-0
R/W-0
7
6
GIG
TXPACE
GMIIEN
R/W-0
R/W-0
R/W-0
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 68. MAC Control Register (MACCONTROL) Field Descriptions
Bit
Field
31-18
Reserved
17
GIGFORCE
16-15
Reserved
14
RXOFFLENBLOCK
13
RXOWNERSHIP
12
RXFIFOFLOWEN
11
CMDIDLE
10
Reserved
9
TXPTYPE
8
Reserved
7
GIG
6
TXPACE
110
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Figure 69. MAC Control Register (MACCONTROL)
Reserved
R-0
13
RXOWNERSHIP
RXFIFOFLOWEN
R/W-0
5
4
TXFLOWEN
R/W-0
Value
Description
0
Reserved
0-1
Gigabit force mode. This bit is used to force the EMAC into gigabit mode, if the MTCLK input
signal has been stopped by the PHY.
0
Reserved
Receive offset/length word write block.
0
Do not block the DMA writes to the receive buffer descriptor offset/buffer length word.
1
Block all EMAC DMA controller writes to the receive buffer descriptor offset/buffer length
words during packet processing. When this bit is set, the EMAC will never write the third word
to any receive buffer descriptor.
Receive ownership write bit value.
0
EMAC writes the Receive ownership bit to 0 at the end of packet processing.
1
EMAC writes the Receive ownership bit to 1 at the end of packet processing. If you do not use
the ownership mechanism, you can set this mode to preclude the necessity of software having
to set this bit each time the buffer descriptor is used.
Receive FIFO flow control enable bit.
0
Receive flow control is disabled. Full-duplex mode: no outgoing pause frames are sent.
1
Receive flow control is enabled. Full-duplex mode: outgoing pause frames are sent when
receive FIFO flow control is triggered.
Command Idle bit.
0
Idle is not commanded.
1
Idle is commanded (read the IDLE bit in the MACSTATUS register).
0
Reserved
Transmit queue priority type.
0
The queue uses a round-robin scheme to select the next channel for transmission.
1
The queue uses a fixed-priority (channel 7 is highest priority) scheme to select the next
channel for transmission.
0
Reserved
Gigabit mode bit.
0
Gigabit mode is disabled; 10/100 mode is in operation.
1
Gigabit mode is enabled (full-duplex only).
Transmit pacing enable bit.
0
Transmit pacing is disabled.
1
Transmit pacing is enabled.
Figure 69
and described in
12
11
CMDIDLE
Rsvd
R/W-0
R/W-0
3
RXBUFFERFLOWEN
Rsvd
R/W-0
www.ti.com
Table
68.
18
17
GIGFORCE
Reserved
R/W-0
10
9
TXPTYPE
Reserved
R-0
R/W-0
2
1
LOOPBACK
FULLDUPLEX
R-0
R/W-0
R/W-0
SPRUEQ6 – December 2007
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16
R-0
8
R-0
0
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