Mdio User Command Complete Interrupt (Masked) Register (Userintmasked); Mdio User Command Complete Interrupt (Masked) Register (Userintmasked) Field Descriptions - Texas Instruments TMS320DM646x User Manual

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4.8

MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in
Figure 34 and described in
Figure 34. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
31
15
LEGEND: R = Read only; R/W = Read/Write; W1C = Write 1 to clear, write of 0 has no effect; -n = value after reset
Table 32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
Bit Field
31-2 Reserved
1-0 USERINTMASKED
SPRUEQ6 – December 2007
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Table 32.
Reserved
Reserved
R-0
Field Descriptions
Value Description
0 Reserved
0-3h Masked value of MDIO User command complete interrupt. When asserted, a bit indicates that
the previously scheduled PHY read or write command using that particular USERACCESS
register has completed and the corresponding USERINTMASKSET bit is set to 1.
USERINTMASKED[0] and USERINTMASKED[1] correspond to USERACCESS0 and
USERACCESS1, respectively. Writing a 1 will clear the interrupt and writing a 0 has no effect.
0 No MDIO user command complete event.
1 The previously scheduled PHY read or write command using MDIO user access register n
(USERACCESSn) has completed and the corresponding bit in USERINTMASKSET is set to 1.
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
R-0
MDIO Registers
16
2 1 0
USERINTMASKED
R/W1C-0
77