Emulation Control Register (Emcontrol); Fifo Control Register (Fifocontrol); Emulation Control Register (Emcontrol) Field Descriptions; Fifo Control Register (Fifocontrol) Field Descriptions - Texas Instruments TMS320DM646x User Manual

Ethernet Media Access Controller (EMAC) Registers

5.31 Emulation Control Register (EMCONTROL)

The emulation control register (EMCONTROL) is shown in
31
15
LEGEND: R = Read only; R/W = Read/Write; -n = value after reset
Table 70. Emulation Control Register (EMCONTROL) Field Descriptions
Bit Field Value
31-2 Reserved 0
1 SOFT 0-1
0 FREE 0-1

5.32 FIFO Control Register (FIFOCONTROL)

The FIFO control register (FIFOCONTROL) is shown in
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 71. FIFO Control Register (FIFOCONTROL) Field Descriptions
Bit Field
31-23 Reserved
22-16 RXFIFOFLOWTHRESH
15-5 Reserved
4-0 TXCELLTHRESH
114 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
Figure 71. Emulation Control Register (EMCONTROL)
Reserved
Reserved
R-0
Description
Reserved
Emulation soft bit
Emulation free bit
Figure 72. FIFO Control Register (FIFOCONTROL)
Reserved
R-0
Reserved
R-0
Value Description
0 Reserved
0-3Fh Receive FIFO flow control threshold. Occupancy of the receive FIFO when receive
FIFO flow control is triggered (if enabled). The default value is 2h, which means that
receive FIFO flow control is triggered when the occupancy of the FIFO reaches 2 cells.
0 Reserved
0-1Fh Transmit FIFO cell threshold. Indicates the number of 64-byte packet cells required to
be in the transmit FIFO before the packet transfer is initiated. Packets with fewer cells
are initiated when the complete packet is contained in the FIFO. This value must be
greater than or equal to 2 and less than or equal to 24 (2
Figure 71 and described in
R-0
Figure 72 and described in
23 22
RXFIFOFLOWTHRESH
5
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Table 70.
2 1
SOFT
R/W-0
Table 71.
R/W-2h
4
TXCELLTHRESH
R/W-18h
TXCELLTHRESH
SPRUEQ6 – December 2007
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16
0
FREE
R/W-0
16
0
24).